In order to overcome the problems of high latency, high computational complexity and high hardware structure complexity of successive cancellation (SC) decoding algorithm in 5G mobile communication systems, the freezing bit design pattern was proposed based on frozen bit, frozen bit pair and frozen interval. The design pattern included the analysis method of decoding latency and calculation complexity. The SC decoding tree was further simplified by preferentially pruning frozen bit nodes, thereby speeding up the search decoding tree. An improved pipelined tree SC decoder with N = 1 024 was implemented based on the FPGA platform. Experimental results showed that the decoding latency was 2.35 μs and the data throughput was 435 Mbit/s. Compared with the existing decoder, the decoding latency and data throughput of the decoder were optimized by 9.6% and 10.4%, respectively.