The structure of NMOS device was improved by optimizing ESD implanted process parameters .The submicron ggNMOS ESD protection circuit unit was tested by transmission line pulse TLP method. The test results showed that the uniformity of electrostatic discharge current was improved after the optimization. The study of the output characteristics of the ESD-implanted NMOS showed that the drain terminal current IDT was a compound current, and it exhibited IDT-VGS differential negative resistance phenomenon under high electric field when gate-source voltage VGS was more than the threshold value VGS0. The theoretical analysis of IDT-VGS differential negative resistance phenomenon from impact ionization and snapback effect at MOS-Bipolar hybrid mode were presented. The research results of this paper could be used to optimize ESD design of CMOS/BiCMOS IC.