Glass has excellent advantages of high-frequency electrical properties, mechanical stability and low cost, making it an ideal material for the next generation of high-density packaging substrates. However, there is a significant difference in the coefficients of thermal expansion between glass and copper, considerable thermal stress is prone to occur during temperature changes, especially near key structures such as through glass vias (TGVs), which affects the performance and reliability of the glass substrate. Aiming at the reliability issue of the glass substrate hole-filling structure, the finite element simulation and experimental methods are used to study the introduction of an organic polymer layer at the interface between glass and copper as a stress buffer layer to regulate the internal stress at the interface and improve its reliability. The influence law of the organic polymer thickness on the thermal stress in glass filling structure is analyzed. The simulation results show that inserting a buffer layer with a thickness of 1 μm can reduce the maximum principal stress of the glass substrate by approximately 40%. The experiments further verify that the thermal stress reliability of the glass substrate with a stress buffer layer has been significantly improved.

Glass substrate has emerged as a key material for advanced packaging due to its superior mechanical properties and high flatness. To reduce the glass core stress, a scheme of sintering an inorganic buffer layer between the TGV glass and copper on the glass substrate is proposed. To ensure compatibility with subsequent electroless metallization processes, simulation analysis is conducted to analyze the effects of three types of inorganic buffer layers, namely ZnO, TiO2, and ZrO2, on the stress distribution of the glass core. At the same time, the influences of buffer layer thickness, glass core thickness, and TGV diameter on the glass core stress are also investigated. The results show that, compared with TGV filled with pure copper, the proposed scheme can effectively reduce the stress of the glass core during the heating process in the lamination stage. Among them, the glass core stress of the sintered 5 m TiO2 is reduced by 66.58%. At the same time, the thicker the buffer layer and the smaller the TGV diameter, the lower the glass core stress during the TGV heating process of the glass substrate. These findings can provide an important reference for reducing the stress of the glass substrate TGV.

With the development of radio frequency (RF) systems towards high frequency and integration, through glass via (TGV) technology has become a core solution to break through the limitations of traditional substrates due to the low dielectric loss and high thermal conductivity of glass substrates. The manufacturing process, RF device integration innovation, and application progress of TGV technology in 5G/6G communication and millimeter wave systems are systematically reviewed. In the field of RF devices, TGV significantly improves the performance density of passive devices such as lumped inductors and capacitors through three-dimensional interconnection, and supports filter design to achieve low insertion loss and miniaturization. In antenna applications, TGV multi-layer stacking technology promotes the expansion of packaged antennas to the millimeter wave frequency band, while improving interconnection density and achieving RF heterogeneous integration through ultra-thin adapter boards and embedded fan out technology. The future development trends include innovations in high aspect ratio through-hole technology, improvement in high-frequency process consistency, and multi physics field collaborative design to break through the performance bottleneck of millimeter wave frequency band, accelerate the large-scale application of TGV in 5G/6G communications, terahertz systems, and intelligent terminals, and provide high-performance and low-cost solutions for RF integration and heterogeneous packaging.

With the continuous development of 3D integration technology, glass-based packaging has begun to be widely researched due to its unique advantages. Bonding technology, as the key and a major challenge of glass-based packaging, is the direct core of constructing “chip skyscrapers”. It must simultaneously meet stringent requirements for physical connection strength, electrical reliability, and thermal compatibility of heterogeneous materials. Based on whether global heating is required, bonding technologies can be categorized into two groups: thermal bonding, represented by thermocompression diffusion bonding and anodic bonding, and room-temperature bonding, represented by ultrahigh-vacuum surface-activated bonding and laser bonding. Surface treatment technologies, including low-vacuum plasma activation, vacuum ultraviolet irradiation activation, and wet-chemical activation, are highly effective in reducing bonding temperature and enhancing bonding success rate. Through a review of the technical principles and characteristics of glass-based bonding technologies, their advantages and disadvantages in diverse application scenarios are evaluated, providing references and ideas for the continuous innovation and development of glass-based bonding technology.

Although the three-dimensional integration technology based on through silicon via can increase the data transmission bandwidth and integration degree, and has outstanding advantages in terms of size, compatibility and performance, it also faces major challenges such as large high-frequency loss and high process cost. Therefore, it is highly necessary to explore the millimeter-wave circuits and system integration technologies based on new substrate materials. Glass or quartz materials can overcome the defects such as high-frequency loss of silicon substrates and are currently relatively ideal substrate materials. Compared with silicon substrates, glass substrates, as low-dielectric insulators, can directly contact metal conductors without the need for an insulating isolation medium layer. Their process complexity and cost are significantly reduced. Their high-frequency electrical properties are more stable, and their coefficient of thermal expansion is similar to that of silicon substrates. When bonding with silicon-based integrated chips, the thermal stress generated is smaller, thereby reducing problems such as warpage and solder joint failure and improving the reliability of three-dimensional packaging. Therefore, the millimeter-wave integrated passive devices (IPDs) based on the glass interposers can achieve good electrical characteristics while maintaining low cost. The development of 3D IPD based on through glass via technology in China is introduced, as well as the influence of parasitic parameters on signal transmission with the development of through glass via technology and the reduction of aperture size.

The increasing demand for data transmission bandwidth and energy efficiency driven by artificial intelligence and high-performance computing highlights the limitations of conventional copper interconnect technology, such as signal attenuation, high power consumption, and significant delays. Co-packaged optics technology achieves heterogeneous integration of photonic integrated circuits and electronic integrated circuits, providing a novel approach to overcoming the bottlenecks of electrical interconnects. The critical role of glass substrates as interposers in co-packaged optics technology is systematically analyzed, and the advantages of low dielectric loss, high thermal stability, wide spectral transparency, and compatibility with optical waveguide fabrication processes are illustrated. Discussions are provided on the ion-exchange technique for fabricating optical waveguides on glass substrates, the design of integrated electro-optical architectures, and representative schemes proposed by leading research institutions. In addition, challenges related to manufacturing yield, thermal management, and standardization coordination in glass substrate co-packaged optics technology are evaluated, and potential applications in data centers and related fields are projected.

Through glass via (TGV) technology, as a key technology for three-dimensional integration and advanced packaging, demonstrates broad application prospects in radio frequency devices, high-density heterogeneous integration devices, and optoelectronic co-packaged devices, owing to its excellent high-frequency performance, low dielectric loss, and superior thermomechanical stability. However, reliability issues with TGV technology remain one of the core challenges hindering the large-scale industrialization. The development history of TGV technology, its current application research status, the fabrication processes of glass interposers, and recent advancements in reliability studies are systematically reviewed. The reliability problems of key TGV interconnect structures caused by processing, design, and thermal stress are particularly discussed. After summarizing common interconnect failure mechanisms, the current shortcomings are highlighted in TGV reliability research, including studies on multi-field coupled failures, collaborative evaluation of multiple performance parameters, and the development of failure analysis methods. In response to the demand for developing next-generation high-performance devices based on TGV technology, key areas requiring further attention in future reliability research are analyzed. Insights and references for subsequent systematic reliability studies on glass interposers and TGV technology are provided.

As Moore's Law gradually approaches its physical limits, the development of electronic devices toward "smaller, thinner, and more precise" dimensions simultaneously imposes higher demands on advanced packaging technologies. Glass substrates have gained significant favor among domestic and foreign enterprises and research institutions due to their advantages, including excellent high-frequency application performance, a flexibly tunable coefficient of thermal expansion (CTE), low cost, and the ready availability of large-size ultra-thin glass substrates. The metallization process, serving as a critical step in through-glass vias (TGVs), determines the electrical connection performance of integrated chips. Currently, TGV metallization is primarily implemented using physical vapor deposition (PVD) technology. However, the high cost, slow deposition rates, and poor effectiveness of PVD in processing high-aspect-ratio blind and through-holes have drawn widespread attention to wet processes for TGV metallization. Addressing this, the deposition mechanism of TGV electroless plating is elaborated upon, recent research advances and key technologies for enhancing adhesion strength between the electroless plated layer and the glass substrate are reviewed, while insights into future development directions are also provided.

With the continuous development of integrated circuits towards high density and performance, through glass via (TGV) interconnection technology has shown broad prospects for applications in three-dimensional electronic packaging, integrated passive devices, and optoelectronic device integration due to its advantages of excellent electrical and optical properties, excellent mechanical reliability, and low cost. A comprehensive review of the application background, manufacturing process, material selection, and key mechanical challenges of TGV in chip packaging is provided. The advantages of TGV over through silicon via technology are summarized in terms of cost, electrical performance, and mechanical stability. The manufacturing process of TGV and glass panel is elaborated in detail, and the differences of mechanical properties among commonly adopted glass materials (silicate glass, quartz glass, and borosilicate glass) are highlighted. A detailed discussion of the mechanical challenges faced by TGV technology is presented, along with potential solutions. The research results can provide a theoretical and engineering reference for optimizing TGV structures and designing high-reliability packaging in future applications.

Advanced packaging technologies are rapidly evolving driven by the quick development of new applications like high-performance computing and artificial intelligence. High-end substrate technology is core support that must concurrently handle the multiple performance requirements, such as high-speed and high-frequency data transmission, power management, ultra-fine-pitch interconnections, and system-level integration. Glass substrates have become a key solution to overcome the limitations of traditional packaging because of their great thermomechanical durability, very low moisture absorption, and exceptional electrical qualities. The structural features and crucial production processes of glass substrates are analyzed, with a special focus on reliability concerns, and the technical opportunities and challenges they faced are summarized.

Ceramic ball grid array (CBGA) packaging technology plays a crucial role in the field of electronic packaging due to its high-density interconnect advantages, and the reliability of solder joints is a key factor affecting device performance. The finite element method is used to investigate the life prediction technology of solder joints under thermal cycling loads. Monitor the on resistance through board level temperature cycling test to analyze the lifes data of solder joints. A finite element model of CBGA solder joints is constructed, and simulation and experimental data are compared and analyzed. The average increment of solder joint strain energy density is determined as the life characterization factor, and the robustness of the model is optimized. The experimental measured data is organically combined with simulation results and integrated into the Darveaux life model, the solder joint life prediction method is established. The research results confirm that this method can effectively predict the life of CBGA solder joints, providing strong technical support for the reliability design of similar packaged products.

Radio frequency (RF) channel isolation is one of the important indicators for measuring the performance of system in package (SiP) modules, which directly affects the stability and signal quality of the system. A ball grid array (BGA) solder ball isolation technology for 3D SiP modules has been proposed, which utilizes BGA solder balls connecting the upper and lower substrates in the board level stacking process to form a shielding wall, thereby improving the isolation between RF channels. The common RF space leaks in SiP modules are classified according to their arrangement, and the effectiveness of this isolation technology is verified through simulation calculations and physical testing, providing strong support for improving the RF channel isolation of SiP modules.