A foreground calibration technique for current source mismatch in ultra-high-speed DAC was presented. Two calibration sub-DACs were designed. The calibration currents provided by the two DACs were used to compensate the two components of the current source mismatch. Each calibration DAC had the same temperature characteristics as its corresponding mismatch part. Therefore, the total calibration current could automatically track the temperature changes. The two calibration sub-DACs used two different bias currents to replace different temperatures, and then the calibration number was obtained by the designed calibration algorithm. The calibration scheme could effectively reduce the calibration time and improve the temperature stability of the front calibration. A 16-bit 12 GS/s current-steering D/A converter designed in a standard 65 nm CMOS process validated this calibration technology. The test results show that the SFDR of the DAC reachs 65 dBc at 1 GHz analog output. After calibration, the change rate of DNL is less than 8%, and the change rate of INL is less than 5% in the range of -55 ℃ to 125 ℃. Compared with other similar calibration techniques, this calibration technique could achieve better temperature stability.

Based on the traditional Doherty power amplifier, a MMIC Doherty power amplifier with high back-off efficiency for 5G communication in N79 band (4.4~5 GHz) was designed in a GaAs heterojunction bipolar transistor (HBT) process. By using cascode structure in Doherty circuit and adding common-base grounding capacitor in cascode structure, the gain and output power of DPA were greatly improved. Lumped elements were used to participate in the matching, which reduced the area of the chip. The simulation results show that in the target frequency band, the gain is greater than 28 dB, the saturation output power is about 38 dBm, the saturation added efficiency (PAE) is 63%, and the efficiency of 7 dB output power back-off is 43%.

A high frequency ultra-wideband digital step attenuator with low insertion loss and large attenuation range was designed and implemented in a 65 nm CMOS process. Bridged-T and π-type switch embedded attenuation structure was adopted for good port matching performance and high attenuation accuracy. Constant negative voltage bias was adopted to reduce insertion loss and improve ultra-wideband performance. Cascade design of attenuation cells with high matching was adopted to realize high attenuation accuracy under large attenuation range. The measured results show that the maximum attenuation value is 31.5 dB, the attenuation step is 0.5 dB, the insertion loss of reference state is less than 3.5 dB, and the rms of amplitude error is less than 0.45 dB at 10 MHz~30 GHz. The total chip size is 2.30×1.20 mm2.

A 25 Gb/s optical receiver front-end amplifying circuit was designed in a 0.13 μm SiGe BiCMOS process. This amplifying circuit realized the monolithic integration of the front-end amplifier circuit of the optical receiver. The transimpedance amplifier with feedback system, inductance peaking technology, automatic gain control circuit and other disign were adopted to improve the gain, bandwidth and system stability effectively. The results of simulation and experimental test show that the gain is up to 69.9 dB with a bandwidth of 19.1 GHz. Moreover, the bandwidth error is kept less than 0.1% under the industrial-grade working temperature (-40 ℃~+85 ℃). The power supply current is 45 mA with the power consumption of 81 mW, and the jitter RMS (root mean square) value is 5.8 ps, which indicate a good performance and stability. This design proposes a design method that can be applied to 100 Gbit/s (25 Gbit/s×4 lines) optical interconnection system, which has a broad application prospect.

To solve the problem that silicon-based millimeter-wave power amplifier (PA) have low saturation output power, insufficient gain and low efficiency, a continuous class-F PA with high efficiency and high gain operating at 28 GHz was designed in TSMC 40 nm CMOS process. The proposed PA consisted of driver stage and power stage, where a transformer-based harmonic control network was designed to achieve power combining and harmonic suppression, which effectively improveed the saturated output power and power-added efficiency. Additionally, the PMOS capacitance was used to offset the gate-source capacitance of the power stage, further enhancing the linearity and gain. The post-simulation results show that the designed PA has a peak power-added efficiency of 54% at the saturated output power of 20.5 dBm, with the 1 dB compression point of 19 dBm, and power gain of 27 dB. In the frequency ranging from 24 GHz to 32 GHz, the power-added efficiency is greater than 40%.

Machine learning for integrated circuit hardware Trojan horse detection can effectively improve the detection rate. Unsupervised learning methods still have shortcomings in feature selection. At present, the research work mainly focuses on supervised learning methods. In this paper, the new characteristics of ring oscillator Trojan horse was introduced, and the hardware Trojan horse detection method based on unsupervised machine learning was studied. Firstly, the 5-Dimensional eigenvalues of each node were extracted for the circuit netlist to be tested. Then the local outlier factor of each node was calculated by LOF algorithm to screen out the hardware Trojan horse nodes. The simulation results of Trust-HUB reference circuit show that compared with the existing detection methods based on unsupervised learning, TPR (true positive rate), P (accuracy) and F (measurement) are improved by 16.19%, 10.79% and 15.56% respectively. The average TPR, TNR and A of hardware Trojan horse detection for Trust-HUB reference circuit reach 58.61%, 97.09% and 95.60% respectively.

A new output harmonic control structure was adopted for solving the influence of transistor parasitic parameters on the efficiency of the inverse class F (F-1) power amplifier. Firstly, the second and third harmonic control circuits were designed, and the direct current bias circuit was added into the second harmonic control circuit, which reduced the complexity of circuit design. Secondly, in order to solve the influence of parasitic parameters on the intrinsic drain impedance of class F-1 power amplifier, a serial microstrip line was used for parasitic compensation. Finally, the fundamental wave and load were matched through microstrip lines and capacitors. In order to verify the effectiveness of the method, a 0.25 μm gallium nitride high electron mobility (GaN HEMT) transistor technology was adopted to design an class F-1 Monolithic Microwave Integrated Circuit (MMIC) power amplifier working at 5.7 GHz~6.3 GHz. The post-layout simulation results show that the drain efficiency (DE) and power added efficiency (PAE) of class F-1 power amplifier are 57.2%~62.3% and 51.8%~57.4%, respectively. The saturated output power is 39.0 dBm~40.4 dBm, the gain is 9.0 dBm~10.4 dBm, and the layout area is 3.2×1.7 mm2.

A fractional-N cascaded PLL with low jitter, fine frequency resolution, as well as fast-locking feature is proposed. An MDLL and a Delta-Sigma modulator (DSM) based on phase selector were adopted to achieve fractional frequency multiplication. Following that, a wideband integer-N PLL was employed to not only further multiply up the output frequency, but also filter away the residual DSM quantization noise. Implemented in TSMC 65 nm CMOS process, the overall PLL occupied a die area of 0.27 mm2 and covered the frequency range of 1.064 to 1.936 GHz. With the input frequency of 100 MHz, the PLL achieves locking within 300 ns when the output is 1.872 GHz, and the overall power consumption is 8.6 mW under 1.2 V supply voltage. The frequency resolution is about 1 kHz, and the RMS jitter is 1.32 ps in the integration range of 1 kHz to 100 MHz.

An off-chip large capacitor fast transient response low dropout regulator was designed. The LDO introduced a push-pull structure in the output with the translinear circuit, which effectively reduced the amplitude and recovery time of the overshoot, and improved the transient response speed. The floating buffer was used to drive the power transistor, which effectively improved the LDO’s current efficiency. Dynamic zero compensation technology was adopted to ensure the loop stability of LDO in the all load conditions. The LDO was designed and simulated based on the 0.35 μm BCD process. The results show the input voltage range of the LDO is in 1.2 V~3 V, the output voltage is 1 V, the quiescent current is about 50 μA, and it can provide 0~3 mA load current. During load transients with 500 ns rising and falling edges, 300 mA amplitude, 50 μs light load durations, the overshoot and undershoot are less than 20 mV, which meets the application requirements of high frequency load transition.

In order to meet the application requirements of the e-GaN half-bridge gate driver with multi-MHz frequencies, a low FOM level shifter with high speed, high reliability and low power consumption is proposed. The series controllable positive feedback level shifter ensured low transmission delay and high common mode transient immunity (CMTI) by only weakening the positive feedback during the conversion process, and a minimum short pulse circuit was adopted to reduce power consumption at the same time. The level shifter was designed and simulated in a 0.5 μm 80 V high voltage (HV) CMOS process. The results show that the circuit has a propagation delay of 960 ps, a CMTI of 50 V/ns, and an FOM value of 0.024 ns/(μm·V).

A high-speed, low-power-consumption L-band charge-pump phase-locked loop (CPPLL) with multi-input frequency selection and multilevel output frequency modulation range was designed in SMIC 180 nm/1.8 V CMOS technology. A 4-to-1 data selector was added at the input end to realize tracking and phase-locking of signal at multi-frequency point. At the output end, a programmable dual-modulus prescaler based on a novel P/S type counter was designed to realize high-precision frequency division and programmable continuous bit output. The experimental results show that, the locking time from startup to stabled 1.1 GHz output is 1.5 μs and the power consumption can be lowered to 1.2 mW. In addition, the 2~15 bits continuous programmable frequency division can be realized with frequency tuning range of 73 MHz to 500 MHz. Finally, the layout design of the overall PLL circuit is implemented and the area is only 0.027 mm2, which had been transferred to SMIC for chip tapeout. The proposed L-band PLL can be effectively employed in wireless communication and RF signal processing systems, such as satellite down-frequency-receiving, optical signal modulation and digital audio broadcasting (T-DAB).

With the development of quantum computers, traditional encryption algorithms are seriously threatened. In order to combat with quantum attacks, homomorphic encryption technology has received attention increasingly. Among them, the ring-learning with error (R-LWE) encryption scheme has the advantages of high encryption efficiency and simple hardware implementation as well as huge potential in hardware encryption. This paper proposes and implements an RLWE encryption and decryption circuit structure, which uses Fermat number transforms (FNT), memory access optimization and time division multiplexing methods. The results show that under the equivalent security parameter set, in the terms of the encryption and decryption function, The hardware resource efficiency of the RLWE encryption and decryption circuit can reach 6.01 and 12.03 respectively.

An active and passive dual-mode ROIC based on HgCdTe-APD in linear mode was designed. In passive mode, the intensity of optical signal was measured by integral capacitance, and in active mode, the photon time of flight (ToF) was marked by two-segment TDC. TDC used the low-segment digital counter shared by the array for rough counting, and the pixel-exclusive time-amplitude conversion circuit (TAC) circuit for fine measurement. Simultaneously, the time walk error was corrected by switching integral capacitance. Based on SMIC 0.18 μm CMOS process, the proposed 32×32 LM-APD array ROIC was designed and fabricated, and the operating temperature was 77 K. The simulation results show that the full well capacity of the circuit is 7.5 Me-. The ToF resolution is reduced to < 0.5 ns with a wide range of 3.2 μs. The differential non-linearity (DNL) is restricted to -0.15 LSB~0.15 LSB, and the integral non-linearity (INL) is -0.2 LSB~0.2 LSB. The power consumption is less than 180 mW under a frame rate of 4.5 kHz.

An LDO with fast transient response characteristics for off-chip large capacitance scenarios is proposed. The circuit was constituted with a high bandwidth voltage buffer by adopting the structure of negative feedback for load current sampling. A cascode compensation structure with capacitance multiplication function was used. Under the condition of external 1 μF load capacitance, only 500 fF on-chip compensation capacitance could ensure stability in the full load range. By using adaptive biasing technology, the transient response speed was further improved while reducing light-load power consumption. The circuit was designed and simulated in 0.18 μm CMOS process. The simulation results show that when the input voltage of the LDO is 1.2 V and the output voltage is 1 V, the overshoot and undershoot voltage are 10.7 mV and 8 mV respectively under a step load change from 150 mA to 100 μA within 0.7 μs.

Memristor is an emerging non-volatile memory, which has several remarkable features such as simple structure, low power consumption, high integration density, and synaptic-like behaviour. Memristors have been primarily proposed to function as artificial synapses for constructing artificial neural network in the form of crossbar array. However, the crossbar array of memristors is confronted with severe potential path sneak currents issue, resulting in a large obstacle to further applications of memristors. In this paper, the causes of sneak currents issue in stacked crossbar array of memristor were analyzed briefly. The solutions, such as One Diode-One Resistor(1D1R), One Selector-One Resistor(1S1R), and One Transistor-One Resistor(1T1R), to suppress sneak currents were demonstrated. The promissing future of memristor with very large scale integrated crossbar array for various application was anticipated.

The causes of VLSI design rule check violation (DRC) in advanced technology are very complex, which makes the congestion map of global routing can’t reflect the distribution of DRCs accurately. In this paper, a deep-learning based approach is proposed for predicting DRCs. Pin, net and macro information of placement rather than global routing were used as features. Then, these features were trained by a convolutional network after being processed by CSMOTE. Finally, M2 short and cut group space were predicted by this model. The method was tested in a real industrial design in advanced technology node. Experimental results show that the accuracy and F1 score on M2 short is 93.4% and 0.78 respectively, while 92.5% and 0.78 on cut group space.

The total ionizing dose (TID) effect of Nb∶SrTiO3 resistive switching cells and 1T1R structures were investigated by using X-rays. The experimental results show that the Nb∶SrTiO3 cells exhibit superior radiation tolerance exceeding 10 Mrad(Si) after which the resistive switching properties sustain well and the resistance states do not flip. However, the 1T1R structure is much more susceptible to ionizing radiation due to the performance degradation of NMOS access transistor. The radiation-induced positive oxide-trapped charges can result in the negative threshold shift and increase the leakage current of NMOS transistors, which leads to the unexpected read/write operation of the Nb∶SrTiO3 cell at “off” state(VG=0 V). Therefore, the radiation tolerance of 1T1R structure can be improved significantly by using hardened NMOS transistors.

The transient dose rate effect of the DC/DC converter based on PWM controller with feature of 0.35 μm was studied under pulsed laser. The DC/DC converter was irradiated by a laser with spot diameter of 10 mm, wavelength of 1 064 nm, pulse width of 10 ns and energy from 3 μJ to 2 400 μJ. The responses of DC/DC converter under different energy laser were monitored and compared with the experimental results of pulsed γ-ray. The experimental results show that the output disturbance time of DC/DC converter is about 4.3 ms under the 3 μJ to 577 μJ laser and the output locking threshold of DC/DC converter is about 1 031 μJ.

The traditional dual-directional SCR (DDSCR) have latch-up effect due to low holding voltage. In this study, a novel DDSCR with a high holding voltage was proposed. The floating and highly doped N+ and P+ active regions were added between the anode and cathode of the traditional device. The well in the P+ active region was recombined with electrons in the well and the N+ active region forced the current to bleed through the SCR path of lower resistance deep in the device, then the problem of low holding voltage of the traditional device was solved. Simulation based on TCAD results show that compared with the traditional DDSCR, the holding voltage of the novel device is increased from 2.9 V to 10.5 V. By extending the critical dimension D7, the holding voltage of the device can be further increased to 13.7 V. This device is suitable for chip protection with positive and negative voltages on I/O ports.

The L-band power amplifier (PA) die has a demand for power increase, while facing the problem of large volume. A 300 W die of the GaN HEMT was developed based on 0.5 μm process. The best input and output impedance points of the model were extracted by loadpull simulation. The L-C network was designed with a high dielectric constant thin-film circuit to raise the input and output impedance of the chip and offset the imaginary part. The four-cell core was combined with the two-stage impedance transformed wideband power divider and combiner circuit by using microstrip circuit. A high integrated and miniaturized PA was achieved by building in the stabilization circuit, the gate and drain bias circuit, and achieving a 50 Ω input and output impedance matching. With a total gate width of 4×40 mm, the output power is from 60 to 61.2 dBm, the efficiency is from 57.9 % to 72 % and the saturation power gain is greater than 14 dB under the conditions of a drain voltage of 50 V, a pulse width of 40 μs and a duty ratio of 4%.

The total dose, single event particle and coupling irradiation effects of GaN-based DC/DC converter were investigated. The variation of output voltage, output current and output efficiency of DC/DC converter with different irradiation conditions under specific load and voltage conditions were discussed. The experimental results show that the DC/DC converter using GaN MOSFET switch tubes exhibits excellent anti-irradiation performance under total dose, single event particle and coupled irradiation conditions, i.e., the performance of output voltage, output current and output efficiency of the device do not degrade significantly under three different irradiation conditions. The GaN-based DC/DC converter exhibits super resistance to total dose irradiation greater than 1 kGy (Si) and resistance to single event particle with LET ≥ 75 MeV·cm2·mg-1, which indicates that this type of DC/DC converter has great potential applications in the future for power supply systems in aviation and aerospace.

Due to NJFET’s poor consistency of saturated current in fabrication, experimental studies were conducted on saturation current process influencing factors from first oxidation, gate implantation and gate annealing process, and process optimization and control methods were proposed, resulting in effective control of device saturation current parameters. The stability is improved from 6.9% to 0.38% and the yield is increased from 85% up to 96%, which significantly improve the product quality and reduced the cost.

A novel combined helical piezoelectric energy harvester is proposed. The bottom of this harvester was a right-angle spiral structure, and the top of this harvester was an arc spiral structure. The arc spiral structure was attached to the mass block of the right-angle spiral structure. Four structures can be obtained by rotating the arc spiral with 90 degrees, and the angles are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. The design of the right-angle spiral structure could reduce the resonant frequency, and the design of the arc spiral structure could not only reduce the resonant frequency, but also enable the overall structure to perform multi-directional energy harvesting, thereby increasing the output. The thickness of the single cantilever beam structure was 1 mm and the width was 6 mm. According to the calculation and the simulation, when the combined angle of the two structures is 180 degrees, the maximum output voltage is 13 V and the maximum output power is 1.3 mW.

In order to improve the heat transfer efficiency and the performance of the thermoelectric microwave power sensors, the substrate structure of the thermoelectric microwave power sensors was optimized, and the optimal substrate structure size was obtained in this work. Firstly, the influence of substrate thickness on thermoelectric microwave power sensors was studied. Then, according to the obtained optimal substrate thickness, the effects of substrate position and size on the performance of thermoelectric microwave power sensor were studied. Finally, the microwave characteristics and electromagnetic field distribution of the sensor with the optimal substrate structure were studied. The results show that when the structure size of the sensor substrate is optimal, the maximum temperature of the sensor reaches 352.76 K and the S parameter is less than -20.62 dB. The structure not only reduces the heat dissipation in the substrate and improves the heat transfer efficiency from the load resistance to the thermopile, but also has good microwave characteristics.

The total ionizing dose effect of 22 nm bulk silicon nFinFET was investigated by 60Co γ irradiation experiment. The variation of total dose radiation damage with irradiation bias and device structure was obtained, and the damage mechanism was revealed. The experimental results show that the threshold voltage of the device shift positively after ON bias irradiation, while the threshold voltage of the device shift negatively after TG and OFF bias irradiation. The threshold voltage degradation of the device with fewer fin number is greater than that of device with more fin number. By analyzing the action process of trap charge induced by irradiation, the reason for the above experimental phenomenon is revealed.

In order to solve the reliability problem of power module working under temperature cycle, the transient temperature distribution model and the transient thermal coupling model of power module under temperature cycle were established based on finite element software, and the vulnerable areas such as chip and glass insulator were analyzed emphatically. The maximum thermal stress of the glass insulator and the maximum temperature of the chip were taken as the optimization objectives, and the power module was optimized by genetic algorithm. The results show that compared with other studies, the power module obtained by transient thermal coupling is more accurate, the chip temperature is 86.03 ℃, and the thermal stress of the glass insulator is 61.27 MPa. The temperature of the chip optimized by genetic algorithm is 81.85 ℃, and the thermal stress of the glass insulator is 37.05 MPa, which meet the reliability requirements. It is proved that the combination of genetic algorithm and simulation can effectively improve the reliability of product design.

The reliability problems caused by chip aging are becoming more and more serious, which continuously reduce the performance of the chip and may eventually lead to the failure of the chip. This paper presents a low-overhead aging measurement scheme of bypass reconfiguration Oscillating Ring (RO). The experimental results show that, compared with the existing schemes, the hardware overhead of the scheme is reduced by 63.2%, the performance is improved by 15.7%, and the aging online measurement error is as small as 2%.

The basic principles of various test techniques for measuring the junction temperature of GaN-based light-emitting diodes (LED) were studied, including the pulse current method, the small current method and the optical imaging method. The reliabilities of different methods were compared. The results show that, at a large pulse current, the series resistance effect cannot be ignored, which leads to a rather lower average junction temperature. The small current method is able to reduce both the switching time between the heating current and the test current and the series resistance effect, which improves the measurement accuracy. The optical imaging method is based on the relationship between the light intensity and the junction temperature, which allows to obtain the spatial distribution of the temperature of devices, and could be helpful for fabricating high-quality LED.