Microelectronics, Volume. 52, Issue 6, 942(2022)

Design of a High Efficiency Power Amplifier Based on 40 nm CMOS Process

XU Leijun, MENG Shaowei, and BAI Xue
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    To solve the problem that silicon-based millimeter-wave power amplifier (PA) have low saturation output power, insufficient gain and low efficiency, a continuous class-F PA with high efficiency and high gain operating at 28 GHz was designed in TSMC 40 nm CMOS process. The proposed PA consisted of driver stage and power stage, where a transformer-based harmonic control network was designed to achieve power combining and harmonic suppression, which effectively improveed the saturated output power and power-added efficiency. Additionally, the PMOS capacitance was used to offset the gate-source capacitance of the power stage, further enhancing the linearity and gain. The post-simulation results show that the designed PA has a peak power-added efficiency of 54% at the saturated output power of 20.5 dBm, with the 1 dB compression point of 19 dBm, and power gain of 27 dB. In the frequency ranging from 24 GHz to 32 GHz, the power-added efficiency is greater than 40%.

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    XU Leijun, MENG Shaowei, BAI Xue. Design of a High Efficiency Power Amplifier Based on 40 nm CMOS Process[J]. Microelectronics, 2022, 52(6): 942

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    Paper Information

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    Received: Nov. 3, 2021

    Accepted: --

    Published Online: Mar. 11, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210420

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