A fractional-N cascaded PLL with low jitter, fine frequency resolution, as well as fast-locking feature is proposed. An MDLL and a Delta-Sigma modulator (DSM) based on phase selector were adopted to achieve fractional frequency multiplication. Following that, a wideband integer-N PLL was employed to not only further multiply up the output frequency, but also filter away the residual DSM quantization noise. Implemented in TSMC 65 nm CMOS process, the overall PLL occupied a die area of 0.27 mm2 and covered the frequency range of 1.064 to 1.936 GHz. With the input frequency of 100 MHz, the PLL achieves locking within 300 ns when the output is 1.872 GHz, and the overall power consumption is 8.6 mW under 1.2 V supply voltage. The frequency resolution is about 1 kHz, and the RMS jitter is 1.32 ps in the integration range of 1 kHz to 100 MHz.