With the vigorous development of 5G, artificial intelligence (AI), the internet of things (IoT), and the shrinking size of semiconductor processes, the data processing capacity and other performance of the terminal and servers processors have increased rapidly, which puts forward new requirements for power management chips. Multi-phase parallel converter has great advantages in low-voltage and high-current working condition, fast transient response, etc., and is considered one of the best solutions to the power management challenge of the processors. Starting from the principle and advantages of multi-phase buck converters, the development and latest research progress of key technologies, such as multi-phase current balancing methods, control modes and efficiency improvement, were studied. Finally, the key development trends and challenges of multi-phase buck converters were showed.

With the development of Internet of Things (IoT) technology, more and more IoT sensors are used in environmental monitoring, logistics management, manufacturing, medical care and other fields. The service time of these IoT sensors depends on the service time of the internal battery, which is not removable. Once the battery is damaged or the power is exhausted, it needs to be replaced with a new IoT sensor which greatly increases the cost. The development of energy harvesting technology provides a novel direction for solving the problem. Eliminating the need for batteries, the technology collects weak energy from the environment and converts it into electricity to power IoT sensors through related technologies. This paper summarized the key technologies of the energy harvesting system, compared the advantages and disadvantages of different circuit structures, and summarized the maximum power tracking technology (MPPT). It shows that MPPT technology has developed from one-dimensional MPPT technology to three-dimensional MPPT technology, and now more assistive techniques have been developed to improve the tracking accuracy of MPPT circuits. In order to achieve more extensive applications, multiple-input and multiple-output converters have become the focus of research. In this paper, the converter structure of multi-energy-source-input and multi-output-voltage was summarized, and the performance indexes such as static power consumption and dynamic range became the focus of attention.

Based on the structure of forward converter, a real-time adaptive (RTA) leading edge blanking (LEB) circuit was designed. By blanking oscillation time and oscillation amplitude, the optimal blanking time was tracked to realize RTA LEB, which reduced the system size and cost, and the high-frequency development of the circuit was not limited. The output current information without spike oscillation could be obtained by the designed LEB circuit to ensure that the system could respond quickly to the output load change. The circuit was designed in a 0.18 μm BCD process. Simulation results show that the start-up overshoot was only 50 mV without other additional current limiting functions, and the undershoot voltage and overshoot voltage were 519 mV and 578 mV respectively during load steps.

A high-speed, high common-mode transient immunity level shifter suitable for GaN drivers is proposed. The proposed circuit was controlled by the PWM signal and the short pulse, and an accelerating circuit controlled by short pulse improved response speed during level shifting. During high dV/dt transitions and ringing period of floating power rails, the charging and discharging of the parasitic capacitance in level shifter caused output logic errors. To solve this problem, a high-speed low-power cross-controlled noise blanker was adopted to realize high common-mode noise immunity. The circuit was designed in a 0.35 μm high-voltage CMOS process. The simulation results show that the average propagation delay of the level shifter is 1.58 ns with the floating ground at 100 V, the delay mismatch is less than 100 ps, and the common-mode transient immunity reaches 200 V/ns.

A high noise immunity capacitive level shifter suitable for half-bridge GaN drivers is proposed. During dV/dt transitions and ringing period of the floating power rail, the proposed level shifter adopted decoupling switches to completely eliminate the common-mode noise that interfere with output states, and adopted dynamic switches to reduce the differential mode noise caused by circuit mismatch. Moreover, high negative voltage tolerance, sub-nanosecond propagation delay, and low power consumption were achieved by adopting capacitive coupling technology. The circuit was designed in a 0.18 μm high-voltage BCD process. The simulation results show that under the level shifting of 50 V, the common mode transient immunity of the level shifter reaches 200 V/ns, the mismatch tolerance reaches 30% at 200 V/ns slew rate, the negative voltage tolerance is up to -5 V, and the average propagation delay is 0.56 ns.

Aiming at the problem of poor noise of conventional low dropout linear regulator (LDO) with a capacitor, a low noise LDO circuit with foldback current-limit protection was designed in a 180 nm BCD process. A first-order RC low-pass filter was inserted between the reference and the error amplifier (EA) to eliminate the high-frequency noise of the reference output and to cancel the feedback resistance in the traditional LDO circuit to reduce its contribution to the noise. The functions of current limiting and foldback were realized by the foldback current-limit protection circuit, and the reasonable setting of the short-circuit current could effectively prevent the LDO from entering the locked state during the startup or recovery process. The simulation result shows that LDO stably outputs 2 V when the input voltage is 4-5 V, the maximum load is 70 mA, and the over-current limit is 120 mA. In a typical case, the noise power spectrum is 12.7 nV/Hz at 1 kHz, and the RMS noise is 3.6 μV.

A cable voltage drop compensation circuit for topology of active clamp forward converters is proposed. The proposed circuit sensed load current information by sampling the CS pin at a proper moment, and then adaptively adjusted the reference voltage of the error amplifier according to the information, so the load regulation was effectively reduced and the output voltage accuracy was improved. The circuit was designed in a 0.18 μm 40 V BCD process. The simulation results show that, under 3~30 A load current range without cable voltage drop compensation, the overall load regulation of the active clamp forward converter is 9.78 mV/A, while with the proposed cable voltage drop compensation, the load regulation of the converter is reduced to 0.096 mV/A, which is only 0.98% of that without cable voltage drop compensation.

A static model for multiphase interleaving switched capacitor power converter (SCPC) is proposed. The general capacitor-to-capacitor charge transfer behavior was analyzed. The charge redistribution loss and switch conduction loss in SCPC were described as voltage loss in the charge transfer subprocess equivalently. The equivalent output resistance of a switched capacitor power converter at any switching frequency could be predicted easily and accurately. A “proportional current approximation” method was proposed to establish a charge transfer model with a current load. Therefore, the effects of load and output decoupling capacitors on the static characteristics of capacitive power converters could be predicted and analyzed. Compared with the traditional model, the proposed model can accurately describe the static characteristics of the switched capacitor power converter at medium switching frequency. The output voltage ripple of SPCP in multi-phase interleaving control can be predicated as well.

An adaptive dead time control circuit for GaN gate driver is proposed, with low time delay, low power, high speed, and high switching frequency. The switching node voltage was detected by a single-pulse generation circuit to achieve zero static power dissipation. An interlocking circuit was designed to avoid false triggering which may lead to a shoot-through state. The proposed circuit was designed in SMIC 0.18 μm BCD process. The simulation results show that the dead time is adaptively adjusted along with the load. When the dv/dt of switching node voltage is 48 V/ns, which is the worst working condition, the dead time error of the high and low side are only 1.59 ns and 2.69 ns respectively.

An adaptive slope compensation circuit for boost converter was designed. By dynamically detecting the input and output voltages of the boost converter, the circuit generated a ramp voltage following the duty cycle, and optimized the compensation slope. Due to the high-precision subtractor, the slope compensation accuracy was improved to minimize the adverse impact of compensation to the boost converter while eliminating the sub-harmonic oscillations and improving the stability of the boost converter, with little impact on the load capacity and dynamic response speed. The circuit was designed in SMIC 0.18 μm process. The post simulation results show that, under different working conditions, the compensation slope can be adaptively adjusted with the duty cycle at an operating voltage of 3.3 V, and the error to the theoretical compensation slope is 1.39%~2.33%.

A high efficiency power management circuit for ambient vibration energy harvesting system was designed. As the unstable ambient vibration energy and the strong load dependence, the maximum power point tracking (MPPT) technology was used. To address the problem of excessive power loss in the voltage adjustment phase during MPPT operation, a pseudo buck structure topology with a high frequency switching controller was proposed to reduce the switching loss in the voltage adjustment phase, further improving the system efficiency and enabling pre-stabilization to reduce the burden on the later stage power management. The proposed circuit was designed in a 0.18 μm CMOS process. The simulation results show that, the maximum power point tracking efficiency is maintained at 98.55%~99.45% with wide variations of the input vibration energy and the system load. And the system efficiency is improved up to 94.2%.

Three schemes for improving the efficiency of the power amplifier were introduced: Doherty technology, envelope elimination and recovery (EER) technology, and envelope tracking (ET) technology. It is shown that ET technology has significant advantages in term of performance and reliability. In order to save the power loss of envelope tracking technology and improve the performance of envelope tracking system, a hybrid ET power supply was proposed. Simulation and experimental results demonstrate that the proposed ET power supply achieves an output power of 1 W on a 5 Ω load resistance with a power efficiency of 60%. The efficiency and output linearity can keep stable under various input signal, which make it suitable for power amplifier applications.

The control strategy of a four-switch buck-boost converter with constant current/constant voltage modes was studied. When the input and output voltages were close to each other, buck-boost mode was adopted to realize smooth switching between buck mode, boost mode and buck-boost mode by detecting the duty cycle of the power FETs under different relationship between input and output voltages, thus improving the stability of the system. By designing the maximum value selection circuit, the converter could automatically transit from constant current mode to constant voltage mode in charging application, and the mode transition was smooth and stable. The simulation results show that at 24 V output voltage, when the converter switches from buck mode to buck-boost mode, the output under-shoot voltage is 9.2 mV. When the converter switches from boost mode to buck-boost mode, the output under-shoot voltage is 92 mV. The converter can automatically realize smooth conversion between constant current and constant voltage modes in both buck mode and boost mode.

A ripple-based constant on-time control (RB-COT) buck converter with switched current integrator is proposed. The direct feedback loop was compensated by inductor current ripple, and the sample-hold circuit was introduced to improve output accuracy. Furthermore, the switched current integrator circuit replaced the fixed RC filter in the original architecture, effectively improved the transient response of the system at high switching frequency, and achieved both stability and fast transient response for full switching frequency range. Taking the loop stability in the full switching frequency range as the basic design criterion, the buck converter designed in this paper effectively improved the transient response, especially for high-switching frequency. For 1.0MHz switching frequency, the step up/down transient recovery time is reduced by 20 μs compared with fixed RC filter.

An isolated hybrid buck converter for 48 V-1 V system is proposed, utilizing the flying capacitor and transformer to achieve high conversion efficiency in high conversion ratio applications. The hybrid converter combines the switched capacitor converter and the switched inductor converter, in which the flying capacitor is charged with part of the voltage drop to reduce the voltage stress of the power MOS. Since the voltage swing at the switch node is smaller, the switching loss is reduced accordingly. By using lower voltage power MOS, the conduction loss is reduced. Moreover, the isolated hybrid buck converter can achieve soft-switching through timing control, thereby reducing the switching loss of the power MOS, and making the overall efficiency higher. In the isolated hybrid buck converter, the flying capacitor has the function of the DC-blocking capacitor, which can prevent the magnetic bias of transformer. In the typical application, namely input voltage of 48 V, output voltage of 1 V, and switching frequency of 500 kHz, the peak efficiency is 94.84%.

An adaptive time constant matching Gm-C inductor current sensing method is proposed. By comparing the zero-crossing time difference between the SW voltage of buck converter and the Gm-C filtering sensing voltage, the control loop determined whether the Gm-C time constant matched the DCR time constant. A phase/frequency detector was adopted to detect the time difference. The phase/frequency detector also controlled the reversible counter to calibrate the equivalent capacitance of the capacitor array. Finally, the adaptive time constant matching Gm-C inductor current sensing was implemented. Compared with previous works, the calibration process is smooth, and the DC-DC converter can be modulated online under the normal working condition, which can effectively adapt to the change of external conditions, such as temperature, voltage and current, in the operation of the DC-DC converter.

A multi-source energy harvesting power management chip was designed in a high-voltage 0.6 μm CMOS process, which could harvest piezoelectric energy and photovoltaic energy at the same time. The harvesting chip comprised a photovoltaic interface circuit, a piezoelectric interface circuit, and a DC-DC circuit. The global maximum power tracking circuit was used in the photovoltaic interface circuit to reduce the influence of shadows on the harvested photovoltaic energy of the solar panel and to improve the maximum power tracking efficiency. The DC-DC circuit used the control mode with adjustable on-time and frequency to achieve higher efficiency in the broader input power range while maintaining a more minor voltage ripple at the output. The simulation results show that the harvesting chip’s overall average dynamic current is 7.6 μA, and the energy conversion efficiency is the highest at 91.2%. The layout size is 9 623 μm×3 655 μm.

A current comparison based capacitor-less LDO without voltage reference is proposed. The output voltage was converted to current and compared with reference current, so the voltage reference was thus omitted. In addition, an additional gain stage was adopted to enhance the gains and the resolution was improved. An error amplifier with a source feedback compensation network was inserted into the loop to increase the loop gain and thus improve accuracy, and to maintain loop stability over a wide load range while reducing on-chip compensation capacitance. The proposed LDO was simulated in a SMIC 65 nm CMOS process. The stimulation results show that when the load capacitor is 100 pF, the quiescent current is 9.4 μA, the compensation capacitor is only 0.25 pF, the recovery time is less than 1 μs when the load current is switched between 100 μA and 50 mA, and the overshot and undershot voltage of the LDO with (without) active feedback circuit is 131 mV (94 mV) and 99 mV (21 mV), which is reduced by 28% and 79% respectively..

A low noise high PSR low dropout voltage (LDO) was designed in a 28 nm CMOS process. A folded cascode structure was adopted to design the high output impedance and high-gain error amplifier, which reduced the effect of power supply noise on the output. A cascode Miller compensation structure was used to ensure a high phase margin under both light and heavy load, enhancing the LDO loop stability. A noise reduction module was applied to the input of error amplifier, which reduced the impact of noise on the whole LDO circuit. The simulation and analysis with Cadence Spectre show that, under 1.9 V power supply voltage and the load varied from 10 mA to 60 mA, the loop gain is 77.6~91 dB, and the phase margin reaches 76°~79°. The power supply rejection (PSR) and noise were simulated under intermediate load current of 30 mA. The results show that the power supply rejection is -81.9 dB and the low frequency noise (1 kHz) is 258 nV· HZ-1/2. The layout design and post-imitation comparison of the whole LDO circuit were carried out. The results show that the loop gain is 83.2 dB, the phase margin is 78°, the PSR is -78.3 dB, and the low-frequency noise (1 kHz) is 283 nV· HZ-1/2.

For the problem of solder joint cracking in the environmental test of the SOD-323 double-end device in a power supply product, the mechanism of solder joint cracking was studied. Combining with the temperature characteristics of Three-proofing Lacquer, simulation and stress tests under various conditions were carried out. According to the test results, the reliability application solution for the SOD-323 double-end device is proposed.

The performance of magnetic devices such as transformer and inductor significantly affect the parameters of power supply. Aiming at the problems of poor consistency and low efficiency in making the air gap of the magnetic core of E-type transformer, a finite element analysis model was established for different dispensing schemes, and the shear mechanism of epoxy insulating non-Newtonian fluid with high viscosity was analyzed. The results show that the consistency and processing efficiency of the magnetic devices can be improved by reducing the size of the glue dots, or changing the shape and distribution of the glue dots. By using automatic dispensing process to control the radius and center distance of glue dots accurately, a transformer meeting the requirements of inductance is made, which improves the processing efficiency and verifies the correctness of simulation and mechanism analysis. A high-precision and high-efficiency manufacturing process for torus dispensing and magnetic devices was obtained.

The working frequency band of the ambient kinetic energy harvester (KEH) is narrow, so it is difficult to match with the ambient excitation whose frequency is random, thus restricting practicality. The frequency matching method based on frequency self-tuning technology has the advantages of wide frequency matching range, high frequency matching accuracy, and no manual intervention, which is one of the effective technical solutions to solve this problem. By reviewing the home and abroad research progress in recent years, the frequency self-tuning technologies, realization method and specific realization under vibration excitation and rotation excitation were summarized from the principle. Then, the research progress of frequency matching methods based on the combination of frequency self-tuning technology and nonlinear technology were introduced. Finally, the advantages and disadvantages of different frequency self-tuning methods were compared, and the development direction of frequency self-tuning technology was summarized.

At room temperature, graphene has excellent electrical properties such as large molecular adsorption specific surface area, low noise and high carrier mobility. Compared with traditional inorganic oxide gas sensors, graphene gas sensors have the advantages of low operating temperature, low energy consumption and high recovery. This paper reviewed the research progress of two graphene gas sensors. Firstly, NO2 and NH3 graphene gas sensors were studied according to different gas selectivity. Then their sensitivity, gas response sensitivity and response time were analyzed and compared. This analysis and research work has certain reference value for the practical application and popularization of gas sensor.

A high speed segmented Mach-Zehnder modulators (MZM) driver circuit was designed in a 0.13 μm SiGe BiCMOS process. The bandwidth of the driver input stage was expanded by the capacitive negative feedback, and the common-mode output voltage was stabilized by the common-mode feedback, contributing to a variable gain function. The bandwidth of the output stage was extended by the negative Miller capacitance, T-coil and inductive peaking technology. The propagation delay between close output stages was produced by microstrip transmission lines, so a design method of the microstrip transmission lines was presented. The simulation results show that, the maximum operating rate of the proposed driver circuit is 50 Gbit/s, the voltage output swing is 3 V and the propagation delay between close output stages is 4.9 ps. The driver circuit is well suited for segmented MZM.

The method of nested Miller compensation using dual zero-regulator resistors was proposed, and a large-capacitance drive amplifier with a high-gain feed-forward transconductance stage was designed. The amplifier achieved high gain-bandwidth product and large phase-angle margin without requiring stringent passive compensation component matching requirements, thus enhancing the design system's immunity to process, voltage, and temperature variations. The proposed amplifier had a simple topology and it could be applied to amplifiers with rail-to-rail input and output. A design example of a three-stage rail-to-rail class AB amplifier was presented based on 0.35 μm CMOS process, and the performance of the amplifier was tested. The test results show that under the condition of 200 kΩ resistive load and 600 pF capacitive load in parallel, the gain bandwidth product is 4.4 MHz, the phase angle margin is 85°, the power consumption is 3.6 mW, and the THD is 0.25%. The amplifier is suitable for high output drive.

A high-speed asynchronous FIFO chip was designed in a 0.18 μm CMOS technology for 100 Gbit/s Ethernet PCS link system. Dual-port 8-transistor architecture instead of register in the memory cell was employed to increase transmission rate. Sense amplifier adopted latch-base amplifier combined with pre-charge technology to amplify the tiny signal between bitlines in reading phase for the smaller transmission latency. In order to reduce the writing time and the reading time, the effect of transistor size on the level flip time was also analyzed and simulated in detail, which not only met the requirement of rate, but also obtained the high reliability signal. The whole chip area including pads was 1.43 mm2. Test results show that the FIFO can operate over 1.05 GHz and the eye diagram of the output signal is clear with the horizontal opening degree reaching 0.91UI. The total power consumption is 143.3 mW at the supply voltage of 1.8 V. The designed FIFO is more suitable for 16×6.25 Gbit/s PCS link system.

A compact branch-line coupler with harmonic suppression is presented. By analyzing the characteristics of stub-loaded transmission lines, it is found that a stub-loaded transmission line with a smaller size can be used to equivalently substitute the quarter-wavelength transmission line in the traditional branch-line coupler. As a result, the size of the branch-line coupler is significantly reduced. Furthermore, due to the transmission zero introduced by the open stubs, the harmonic response of the coupler is suppressed. To validate the idea, the equivalent circuit model was developed, analytical closed-form equations were derived, and circuit simulation results verified the design principles.

In order to improve the intelligence of the shop floor monitoring system and the accuracy of pedestrian detection in working scenes, a method based on computer vision technique is proposed. The task was simplified to regression prediction of centroids and scales by an anchor-free feature detection technique based on advanced semantic information. The feature extraction module obtained multi-scale image features applying 4-stage downsampling convolutional network and fused them. The head detection module was divided into two convolutions to process the feature maps in parallel to obtain centroid heat map and scale information and output the detection results. The results show that the MR-2 on the CityPersons dataset R subset reaches 11.61%, and the MR-2 is improved by 0.6% after adding the offset prediction branch. This proves the excellent performance of the personnel testing method.

The effects of mixed-mode stress damage on the DC performance of SiGe HBT devices were studied, and the changes in 1/f noise characteristics of the devices before and after the mixed-mode damage were compared. It shows that the mixed mode damage produces an interfacial defect Pb at the Si/SiO2 interface, which leads to the increase of the base current in low injection level. On the other hand, the base current in the medium injection region decreases due to the passivation of H atoms of the dangling bonds at polysilicon grain boundries, which leads to the enhancement of current gain. However, the mixed-mode damage defects are mainly located near the intrinsic Fermi level within the silicon band gap, which leads the increase of the SRH recombination component of base current. As a result, the low frequency noise characteristics of the device are not changed.

The stress on the traditional rectangular cantilever beam is not uniformly distributed, for there is a stress concentration area at the fixed end of the beam, which attenuated in the axial direction, thus affecting the polarization effect of the piezoelectric layer. At the same time, the resonance frequency of the energy harvester with the rectangular cantilever beam structure is relatively high. To solve this problem, an energy harvester structure with an “inverted‘ trapezoid structure was proposed, which could effectively expand the polarization region and capture lower-frequency vibration energy. The experimental results show that the output voltage of the energy harvester is 404 mV at 124 Hz, and the output power can reach 41.3 μW with 1g vibration acceleration.

Diode is still widely used in I/O ESD application when the process advances to FinFET technology, though the robustness per unit width of the diode is lower than planar process. This paper detailed ESD performance parameters based on 14 nm FinFET process, such as failure current (It2), failure voltage (Vt2), failure current per unit width (It2/Width) and failure current per unit area (It2/Area) of Gated diode. The tendencies of ESD device characteristics with dimension parameters were given. It is found that the It2/Width decreases while the It2/Area increases with the increase of number of fins (nfin), the multiplication factor along the fin (Fn) and the multiplication factor across the fin (Yarray). The on-resistance is almost not affected by nfin and Fn.