A two-stage cascaded broadband low noise amplifier(LNA)chip with working frequency of 2.0-4.2 GHz was fabricated in Sanan's 0.25 μm E-Mode pHEMT process through ADS simulation software. The chip realized 3.3 V single power supply with resistance bias voltage. At the same time, an improved RLC parallel negative feedback structure was designed to realize broadband matching. The simulation results show that the maximum gain of the LNA is 30.9 dB, and the gain flatness is about ± 0.6 dB. The return loss of input is less than -9 dB, and the return loss of output is less than -12 dB. The noise figure is (1.2±0.14) dB in the frequency band of 2.0-4.2 GHz. The system stability factor K is greater than 2.8 in the whole frequency band, and the area of the chip is 0.78 mm×2.2 mm.

A segmented temperature compensated bandgap reference with high PSRR was designed in Huahong 0.18 μm BCD technology. The circuit was powered by 5 V power supply, and the reference output voltage was 1.256 V. The simulation results show that in the temperature range of -45-+125 ℃, the temperature coefficient of the traditional structure is 2.048×10-5/℃ at the TT corner. The temperature coefficient of the bandgap reference with new piecewise temperature compensation is 3.631×10-6/℃, which is 82.3% lower than that of the traditional structure. The static power consumption is 220 μW. The PSRR can reach -102 dB at low frequency, and the worst PSRR is -30 dB at 350 kHz. The bandgap reference is suitable for analog integrated circuits of high precision and high current switching power supply.

A low-power, high-performance gate voltage bootstrap sampling switch circuit was designed in TSMC 40 nm/0.9 V CMOS process for the application of audio signal sampling. The average power consumption of the overall switch circuit was greatly reduced by a novel shorting-connection topology of bulk-drain of PMOS transistor instead of a clock amplifier module. An NMOS transistor was specifically added to the input terminal and turned on/off along with the switched clock, so the switching linearity could be effectively improved and benefited from the suppressing of the body effect of the core sampling transistor. A sine wave signal, which was 19.53 kHz frequency and 0.3 V amplitude as a simulated audio signal was input into the proposed switching circuit, and then a high-speed data sampling simulation with a 10 MHz sampling frequency was carried out. Compared with the traditional switch circuit structure, four dynamic performance indexes in terms of the effective number of bit (ENOB), signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved by 5.5%, 3.7%, 13.8% and 5.4%, respectively. Meanwhile, the power consumption is reduced by 36.8%.

Based on the analysis of integer-order and fractional-order memcapacitor models, a memcapacitor model with two fractional-orders is proposed. The related characteristics were analyzed. At the same time, this model was applied to active low-pass filter circuit. The time domain and frequency domain characteristics of the filter circuit were simulated and analyzed. The experimental results show that, compared with integer-order memcapacitor models, the proposed fractional-order memcapacitor model can adjust the cut-off frequency of the low-pass filter circuit by changing the fractional-order, and then change the filtering effect of low-pass filter circuit.

A fully differential TIA circuit and optically isolated IGBT drive system was designed in a 0.18 μm BCD IC process. The effects of common mode transient noise on the optical isolation were analyzed, and a fully differential TIA structure for improving common mode transient immunity was proposed. The differential input terminals of TIA were connected with a light shielded PD and a normal PD respectively. The level of differential output terminal of TIA was compared. In this way, only one input of TIA could receive the optical signal to generate the differential mode gain, but the coupling of common mode transient interference in the isolation layer could be transmitted to the two inputs of TIA, so the interference effect of common mode transient would be weakened by CMRR. The narrow pulse filter circuit was added to filter out the short pulse error signal caused by common mode transient interference and further improve CMTI. The simulation results show that the CMRR is 105.4 dB, and the CMTI is 325 kV/μs.

An on-chip high accuracy fully integrated relaxation oscillator was designed based on average-voltage-feedback technology, which overcame the traditional relaxation oscillator's sensitivity to comparator delay, device aging, and flicker noise. In addition, a one-time automatic frequency calibration circuit was designed, which could make the oscillator achieve high accuracy frequency with the help of an external reference clock. Based on UMC 40 nm CMOS process, a 50 MHz high accuracy fully integrated relaxation oscillator was implemented, and the layout and post simulation results of the oscillator were also provided. The core area of the oscillator was 181 μm×218 μm. The post-simulation results show that the presented oscillator can calibrate automatically the output frequency to 50 MHz under different process corners, and the output frequency error is only ±0.47% when the supply voltage changes from 2.2 V to 3.6 V and the temperature changes from -40 ℃ to 125 ℃. Under a typical corner, the power consumption of the oscillator is only 200 μW.

In the era of information explosion, the issues of information security are of broad concern. The physical unclonable function (PUF) and the true random number generator become the basic security primitives, providing a lightweight solution. An entropy source separation model is proposed in this paper, which can separate the delays caused by jitter (the entropy of the true random number generator) and process deviation (PUF entropy) in a ring oscillator. A reconfigurable dual-mode circuit on FPGA was designed, which could reconfigure the PUF circuit into a true random number generator circuit by changing the mode. The proposed structure has the advantages of small resource overhead, large area utilization and low power consumption. The experimental results show that the PUF generated by the proposed structure has excellent performance in stability, uniqueness, and uniformity. The true random numbers generated by the proposed structure have high randomness and unpredictability. In addition, all true random numbers have passed the NIST test.

To meet the application requirements of the weak energy harvesting system for low supply voltage and low power consumption, a low power and small area relaxation oscillator with a low temperature coefficient was designed. The structure of the self-cascode composite transistor was used to replace the large resistance in the traditional beta-multiplier-based current references and the large resistance in the oscillator core circuit that generates voltage reference at the comparator input, so as to reduce the circuit area and improve the integration while achieving low power consumption. Based on a 0.18 μm CMOS IC process, the simulation results show that the oscillator can work normally at a supply voltage of 0.8-1.2 V, with a frequency of 2.2 kHz and a minimum power consumption of 30 nW, achieving a temperature coefficient (TC) as low as 1.03×10-4/℃, and the die area was reduced by at least 70% compared with previous research.

Based on JESD204C protocol, a parallel FEC decoder for 64B/66B link layer was designed. 64 bit parallel scheme was adopted in it, which reduced the requirement of clock frequency. For the shortened (2074，2048) binary cyclic code in the protocol, a fast rotation circuit was designed. This circuit could be used to reduce the complexity of design. According to the functional verification test of Modelsim, the results show that the decoder can send and receive the data, and correct and report the error. On the Design Compiler platform, TSMC 65 nm standard digital process library is used for logic synthesis. The report shows that when the working frequency of the decoder circuit is 500 MHz, the slack time is 0.10 ns, and the speed of single channel data processing can reach 32 Gbit/s.

A level shifter circuit based on the fully integrated GaN SOI platform with high dv/dt immunity and negative rail compatibility was designed. Compared with the traditional level shifter circuits, the low voltage domain of the driving part was consistent with the low voltage domain of the high side part of the circuit through the circuit design, and the negative voltage suppression function was realized. Besides, aiming at the logic signal error caused by the internal capacitor charging and discharging caused by the rising and falling of the half-bridge driving switch node, the part of the circuit on the high side was designed to achieve the ability of immunizing common mode noise. In the 200 V GaN SOI process, the level shift circuit converted the 0-6 V input signal to 200-206 V one. The simulation results show that the level shift circuit has a rise transmission delay of 4.74 ns, a fall transmission delay of 4.11 ns, a compatibility to switch node negative rail to -4 V, and a common-mode noise immunity capability of 100 V/ns.

Frequency-Modulated Continuous-Wave (FMCW) radars are widely used in auto-driving scenarios for measuring the distance as well as the speed of multiple targets. The chirp signals, which linearly modulate the output frequency with respect to time, are usually generated by the means of a Phase-Locked Loop (PLL). Due to the limited bandwidth, traditional sawtooth-like chirp signals suffer from the long ramping down time, which degrading the performance of the radar. A fast chirp generation scheme based on a charge pump with segmented current is proposed in this paper. The linearity of the chirp signal was well proved with the optimal charge pump current, i.e., the optimal loop bandwidth. On another hand, much larger current would be employed in the ramping down scene, for the purpose of shorter ramping-down time. The simulation results show that the chirp generator consumes a power of 31.8 mW under 1.2 V supply voltage, when generating a 19.25 GHz to 20.25 GHz chirp. A maximum ramping down slope of 454 MHz/μs is achieved with the proposed technique, which is reduced by 80% compared with constant charge pump current manner.

A low power SRAM architecture for error-tolerant applications is proposed. By pre-coding the input data, the proposed SRAM architecture reduced the power consumption of SRAM circuit with acceptable loss of precision. A single-ended 8T (SE-8T) SRAM bit cell was designed. The proposed SE-8T cell improve read stability by the using of a read buffer. The write ability of SE-8T was improved by breaking the feedback loop of the cell. Cooperated with the SE-8T, the approximate SRAM worked well under ultra-low supply voltage. The proposed SRAM circuit was simulated in the 40-nm standard CMOS technology. The simulation results show that the stability of SE-8T is high while the power consumption is low. Therefore, the power consumption of the proposed SE-8T based approximate SRAM is very low. At 0.5 V supply voltage, the power consumption of proposed approximate SRAM is 59.86% less than that of conventional 6T under the same operation frequency.

Based on the reconfigurability of FPGAs, a digital circuit-based binary memristor emulator is proposed. Compared with the analog circuit-based memristor emulator, the proposed digital circuit-based memristor emulator was easier to reconfigure and was in good match with the mathematical model on which it was based, which could meet all the required characteristics of a memristor emulator. The and-gate, or-gate, adder, and three-person voter were implemented based on this emulator, and the functions of the emulator and the logic circuits were verified by the Altera Quartus II and ModelSim tools. Furthermore, the circuit schematics, simulations results and FPGA resource consumption were given for all designs. According to the simulation results, this binary memristor emulator has smaller hardware resource consumption and is more suitable for the study of large-scale memristor arrays than other digital circuit-based memristor emulators.

A novel fast circuit analysis method is proposed based on the generalized method of time and transfer constants. Furthermore, all the numerator and the denominator coefficients of the transfer function were discussed, and the zeros and poles of their characteristic equation were systematically summarized. This method shows the following advantages: 1) the system transfer function, zeros and poles can be quickly analyzed without complex calculations, moreover, the accuracy is guaranteed; 2) the analysis is intuitive, which can point out the key factors in the circuit that limit the system bandwidth, and it is convenient to modify the circuit topology; 3) the solution accuracy can be determined according to the demand.

In order to meet the sampling requirements of serial transceiver data with different rates, a wideband low jitter PLL clock was designed based on the reconfigurable charge pump array. To realize low jitter clock output with wide frequency range, the output current of the charge pump array was adaptively matched according to the PLL frequency-multiplier factor. The PLL was designed in a 40 nm CMOS process, and the area was 367*569 μm2. The experimental results show that the tuning range of the PLL is 1~4 GHz, the clock output RMS jitter is 3.01 ps@1.25 GHz and 3.98 ps@4 GHz, and the peak-peak jitter is less than 0.1UI.

A novel two-stage correlation double sampling (CDS) circuit is proposed to remove the fixed pattern noise (FPN) for a compact time of flight (TOF) array detector with the time-amplitude converter (TAC) structure. Each CDS stage only adopted two switch transistors and one sampling capacitor, which was much simpler than the traditional fully differential ones. Fabricated in SMIC 0.18 μm standard CMOS technology, the CDS circuit merely occupied a small area of 40 μm×35 μm and consumed the low static power of 301 μW. Experimental results show that the proposed two-stage CDS circuit has a high linearity of 99.98 % and a wide output swing of 0.9 V under 1.8 V supply. The total FPN is reduced by more than 54%. The proposed CDS scheme can effectively eliminate the FPN from the pixels and column lines on the array, which is very suitable for high-density TAC-based TOF detectors.

Based on the phased array chip amplitude and phase calibration system, a self-calibration algorithm is proposed to improve beamforming quality. After calculating the error of each state, only by traversing the errors of all phased array chip states once, the target state could be screened out and a Look-Up-Table (LUT) could be generated. During screening, the amplitude error and phase error of a single target state and the RMS error of all target states calculated by Coordinate Rotation Digital Computer (CORDIC) were constrained. Then, the phased array chip could achieve 6-bit phase shift (360°) with error (RMS) less than 2° and 6-bit attenuation (32 dB) with error (RMS) less than 0.3 dB. Compared with the exhaustive search and successive approximation methods, the calibration scheme saves LUT generation time. According to the algorithm, a self-calibration chip is designed in a 65 nm CMOS technology with die area of 584 613.16 μm2.

With the reduction of process nodes and the increase of complexity of integrated circuit scale, the logic equivalence check plays an important role in ensuring the correctness of design functions in the process of integrated circuit design. The logic equivalence checking technology of combinational circuits was studied in this paper. Aiming at the problems of DPLL and CDCL algorithms commonly used in this field, an improved algorithm based on Monte Carlo tree search was proposed to solve the satisfiable problem. Through the experiment on a subset of ISCAS85 test set, it is proved that the algorithm has a certain improvement on CDCL algorithm, and the average running time applied to combinational circuit equivalence check is reduced by about 20%.

Driven by the demand of electronic equipment miniaturization, modularization and intelligence for artificial intelligence, aerospace and defense weapons, revolutionary breakthroughs have been made in microsystem packaging technology design and critical process. Novel system level packaging technologies allow integrated devices to work together and communicate at very high speeds. With the full integration of the package and wafer process, the packaging reliability and efficiency have been greatly improved, and the parasitic is significantly reduced. In this paper, the structures and types of microsystem packaging were summarized. The realization method and critical technology of high reliable wafe-level package, ball grid array (BGA) package, system in package (SIP), three-dimensional(3D) stacked packaging and TSV process were discussed, and the developing trends were given.

A technology of the Schottky-drain (SD) combined with the field-plated structure is proposed to realize the reverse blocking applications in Si-based vertical MOSFETs. Based on this technology, two novel vertical MOSFETs, SD-VFP-MOS with a vertical field-plate (VFP) as well as SD-SFP-MOS with a slant field-plate (SFP), are proposed and investigated by two-dimensional simulations. Compared with the MOSFET with a SD (SD-MOS) and the MOSFET with a superjunction (SJ) as well as a SD (SD-SJ-MOS), the proposed SD-VFP-MOS, especially SD-SFP-MOS, exhibits a remarkable improvement of reverse breakdown voltage and nearly none influence on the on-state characteristics. Analyses associated with the distributions of the on-state current density, off-state potential, off-state current density and electric field for all the devices are performed, which reveals the inherent mechanism of the VFP and the SFP to improve the reverse blocking ability. Detailed discussions of the dependence of the reverse breakdown voltage and the field-plate efficiency on the parameters of the field-plated structures are conducted, which could be of great value to the design of SD-VFP-MOS and SD-SFP-MOS.

To effectively solve the problems of small transient bandwidth, serious aperture effect, and high power consumption of phased array radar/antenna, an RF MEMS switch was introduced into the true-time adjustable delay structure, and an adjustable true-time delayer based on the RF MEMS switch was designed. The delay paths with different electrical lengths were selected by MEMS double-throw switches to achieve 5-bit RF signal delay in DC~20 GHz. The geometric parameters of the delay unit were simulated and optimized by using HFSS three-dimensional electromagnetic simulation software. The delay quantities of five switchable delay states are obtained, which are 28.34 ps, 64.76 ps, 101.46 ps, 137.97 ps, 174.61 ps, and 210.98 ps, respectively. The delay step is 36.5 ps, and the overall area is about 5 mm3. Compared with other true-time adjustable delayers, the proposed true-time adjustable delayers has the advantages of multiple controllable bits, a considerable delay bandwidth product and high integration.

A Triple-RESURF LDMOS (TR LDMOS) with segmented P buried layer (SETR LDMOS) is proposed. This structure cut the uniformly doped P buried layer of drain side in the traditional TR LDMOS, and the P-type impurities in the drift region presented a nearly stepped doping distribution from the source to the drain side. This optimization could balance the severe substrate-assisted depletion effect at the bottom of the drain terminal, and improve the breakdown voltage of the device. At the same time, when the device turned on, current transmission path was not obstructed, maintaining a low specific on-resistance. The tape-out results show that the breakdown voltage of SETR LDMOS can reach 813 V with the same drift region length of 65 μm. Compared with TR LDMOS, the breakdown voltage of SETR LDMOS is increased by 51 V, with the same specific on-resistance of 7.3 Ω·mm2.

Based on a 150 mm 0.35 μm CMOS process, in the NMOS and PMOS devices, Polysilicon-Insulator-Polysilicon (PIP) capacitors and N+ type polysilicon resistors with different bending radii on a 50 μm silicon substrate in a uniaxial state, the influence of tension and compression on the changes in electrical parameters of the devices was simulated by using the Silvaco TCAD software. The results show that the uniaxial tensile and compressive bending can make the threshold voltage of NMOS drift 0.46 mV and PMOS 0.33 mV. The drain current changes linearly with the amount of deformation. The coefficient of NMOS compression is -0.132 95, and the coefficient of NMOS tension is 0.006 01. The coefficient of PMOS tension is -0.104 47, and the coefficient of PMOS compression is -0.110 7. The resistance value changes linearly with the amount of deformation. When the doping concentration is 1×1019, 2×1019, 3×1019, 4×1019, 5 ×1019, the coefficient is 247, 498, 766, 1 016, 1 301 respectively. The maximum change of the capacitance value and the initial value do not exceed 0.5%, and the conclusion is that there is no mismatch effect. These results are consistent with experimental changes, demonstrating the correctness of the model and laying the foundation for the development of flexible silicon-based integrated circuits with reduced degradation.

Aiming at the problems of low-frequency band, high insertion loss, and low isolation in the application of traditional RF MEMS SPDT switch, a hybrid SPDT switch was designed. By setting the contact switch and capacitive switch in one path, low insertion loss and high isolation in the L-E band area unit were achieved. By coming up with the snake-like upper electrode structure, the elastic constant of the upper electrode was reduced, and therefore the driving voltage needed to drag down the upper electrode of the switch was reduced. HFSS simulation software system was employed to optimize the RF performance parameters of the hybrid SPDT switch, and COMSOL was employed to conduct stress-displacement analysis on the snake-like upper electrode of the switch. The simulation results show that, within the waveband of DC-90 GHz, the insertion loss of the SPDT switch area unit is lower than 1.5 dB @90 GHz, and the isolation is higher than 52 dB @67 GHz, 29 dB @90 GHz. This switch can be used in wireless communication systems, radar systems, instrument measurement systems, and other fields with high requirements for working frequency band.

In order to reduce the resonant frequency, achieve multi-directional collection, and improve the output performance, a 4π arc spiral piezoelectric energy harvester is proposed. The device performance was improved by analyzing the relationship between device size and output performance. The optimized model was simulated in COMSOL to analyze vibration displacement, stress, and resonant frequency. Compared with the 2π arc spiral piezoelectric energy harvester, the 4π arc spiral piezoelectric energy harvester has a lower resonant frequency and a higher output. The 4π arc spiral piezoelectric energy harvester has a resonant frequency of 48 Hz, an output voltage of 12.3 V, and an output power of 400 μW.

An on-line MEMS microwave power detection system with wide dynamic range was designed. The equivalent model of MEMS cantilever beam was established. The overload power of MEMS cantilever structure was studied theoretically, and the relationship between overload power and beam size was obtained. Based on this relationship, MEMS beams of different sizes were designed to improve the upper limit of system power detection, so as to improve the dynamic range of on-line microwave power detection system. According to the structural parameters of the system, the dynamic range of the system was 0~8.41 W. The simulation model of microwave power detection system was established. The S-parameter simulation results show that the return loss of the system is from -37.61 dB to -46.15 dB and the insertion loss is from -0.28 dB to -0.16 dB at 8~12 GHz. It has a wide dynamic range and good microwave performance. This work has a certain reference value for the research of microwave power detection system based on MEMS beams.

The machine learning method based on static structural features has poor detection results for gate-level Hardware Trojans (HT). A HT detection method based on cascaded structure features is proposed. The features are constructed by co-occurrence matrix and are recognized by a many-to-many stacked long short-term memory (LSTM) network. The experimental results show that this method obtains 93.1% of the average true positive rate (TPR), 99.0% of the average true negative rate (TNR) and 79.3% of F1-score in 15 benchmarks from TrustHub. The experimental results are better than the existing methods.

The behavior of the failure hot spots in GaN based HEMT devices was studied. When VGS > Vth, the drain current ID was mainly the drain-source conduction current IDS, and the transport mechanism was drift. When VGS < Vth, ID was mainly the reverse gate leakage current IGD, and the transport mechanism was Fowler Nordheim tunneling related to conductive dislocations. By analyzing the effects of different VGS and VDS on the hot spot distribution, it was shown that the transverse electric field formed by the depletion channel near the drain side of the gate boundary and the vertical electric field in the barrier layer were the main reasons for the hot spots of IDS and IGD current, respectively. The low-light spectrum of hot spots was measured. According to the critical electric field and the maximum photon energy, the average free path of the electron was about 60 nm.