An LDO with fast transient response characteristics for off-chip large capacitance scenarios is proposed. The circuit was constituted with a high bandwidth voltage buffer by adopting the structure of negative feedback for load current sampling. A cascode compensation structure with capacitance multiplication function was used. Under the condition of external 1 μF load capacitance, only 500 fF on-chip compensation capacitance could ensure stability in the full load range. By using adaptive biasing technology, the transient response speed was further improved while reducing light-load power consumption. The circuit was designed and simulated in 0.18 μm CMOS process. The simulation results show that when the input voltage of the LDO is 1.2 V and the output voltage is 1 V, the overshoot and undershoot voltage are 10.7 mV and 8 mV respectively under a step load change from 150 mA to 100 μA within 0.7 μs.