The recent surge in artificial intelligence (AI) and spiking neural network (SNN) has generated a burgeoning interest among scholars in investigating artificial spiking neurons. This exploration holds immense promise in propelling robots toward attaining human-level intelligence, as well as facilitating autonomous learning and adaptive control. Conventional electronic devices lack the nuanced nonlinear behaviors inherent in neuromorphic systems, necessitating convoluted circuitry and a multitude of components to replicate even the simplest functions of biological neurons, all while consuming substantial amounts of power. Consequently, researchers have turned to the operational principles of biological neurons, devising novel artificial spiking neuron models leveraging emerging technologies like memristors. These innovative artificial spiking neurons offer notable advantages such as reduced power consumption, streamlined structures, and well-established fabrication processes, leading to substantial strides in emulating diverse biological neuron functions. This study comprehensively reviewed and analyzed various implementation strategies for artificial spiking neurons utilizing state-of-the-art neuromorphic devices. Moreover, it delved into the practical application of artificial spiking neurons in achieving neuromorphic perceptual capabilities encompassing touch, vision, olfaction, taste, audition, and temperature sensing. Finally, this work contemplated the future trajectory of this field, envisioning potential advancements and trends. By offering valuable insights and perspectives, this paper aims to serve as a reference guide, inspiring further research and practical utilization of artificial spiking neurons.

The barrier layer of copper interconnects plays a crucial role in preventing diffusion between copper and dielectric materials. These barrier materials must meet specific requirements, including high stability, strong adhesion to copper and dielectric materials, and low resistance. Since the 1990s, tantalum nitride/tantalum (TaN/Ta) has been commonly used as copper barrier layers and liner layers. However, as continuous developments in integrated chip scaling occur, the impact of interconnect delay on chip speed has become increasingly significant. The high resistivity and inability of TaN/Ta to electroplate directly the copper have made it challenge to meet the evolving demands. In this paper, the recent advancements in copper interconnect barrier materials, including metal alloys, self-assembled molecular layers (SAM), two-dimensional materials and high-entropy alloys, were reviewed. Additionally, this paper highlighted the challenges and suggest future research directions.

A 10 bit 120 MS/s high speed and low power successive approximation analog-to-digital converter (SAR ADC) was designed. To address the power consumption of the capacitive digital-to-analog converter (CDAC) module, a dual-level high efficiency switch control strategy that maintains common-mode output was proposed, utilizing capacitive splitting technique combined with a C-2C structure. This structure not only reduced the switching power consumption of CDAC but also eliminated the dependence on the intermediate common-mode level during the CDAC switching process, making it suitable for low voltage processes. In terms of improving the speed, ADC used asynchronous logic for acceleration in its control logic. The comparator adopted a fully dynamic high speed structure, which could achieve a working speed of 3 GHz while ensuring accuracy. For CDAC, redundant bits were inserted to reduce the charging time requirements of high order capacitors. The SAR ADC was implemented in a 40 nm CMOS process and operated at a low voltage of 1.1V. Performance simulations were conducted under various process corner conditions. The results show that at a sampling rate of 120 MHz, the effective number of bits (ENOB) is 9.86 bit, the spurious-free dynamic range (SFDR) is 72 dB, the power consumption is 2.1 mW, and the figure of merit (FOM) is 18.9 fJ/(conv·step).

A 12-bit 3.4 MHz low power digital-to-analog converter (DAC) chip was designed in a CMOS process by using the segmented resistor string structure. Combining the design indicators of the building time and static performance, the "5+7" segmented structure was determined to realize good differential nonlinearity (DNL) and integral nonlinearity (INL) characteristics under the condition of guaranteeing the build-up speed and taking into account the mismatch of resistors. The post-simulation results show that at a speed of 3.4 MHz, the DNL is 0.14 LSB and the INL is 1 LSB at room temperature, and at －40 to 125 ℃, the DNL is 0.6 LSB and the INL is 2 LSB. It shows a total harmonic distortion (THD) of －84 dB and an extremely low power consumption of 378 μW at 3 V voltage. The layout area is reduced to 1.09 mm×0.91 mm.

A multi-stage noise-shaping (MASH) structure interstage op-amp sharing Σ-Δ modulator was designed in a 55 nm CMOS process. A 2-2 MASH structure was used to design the modulator parameters. An improvement had been made to the classical switched-capacitor integrator and applied to the design of the modulator circuit, realizing the sharing of op-amps between the two stages of the modulator, reducing the number of op-amps while achieving high precision, and significantly decreasing the power consumption of the MASH structure modulator. Simulation results show that at a supply voltage of 3.3 V, the modulator have a signal-to-noise-and-distortion ratio of 111.7 dB, a spurious-free dynamic range of 113.6 dB, and a total power consumption of 16.84 mW.

Aiming at the problem that wireless receivers need to amplify the signals of different intensities to different degrees, a variable-gain low noise amplifier operating in the 5G communication band from 3 to 5 GHz was designed in WIN’s 0.15 μm GaAs pHEMT process. The amplifier included two stages of amplification circuits, both of which adopted a self-biased structure to reduce the number of ports, and the continuously adjustable range of the system gain of about 39.3 dB (-3.5-35.8 dB) can be achieved by adjusting the control voltage of the second stage amplification circuit to vary from 0 to 5 V. The footprint is 0.94×1.24 mm2. At a control voltage of 0 V, the system noise is 0.53±0.01 dB, and the gain is 35.5±0.35 dB. At the center frequency point of 4 GHz, the OP1dB is 13.2 dBm, and the OIP3 reaches 32.7 dBm, indicating that the system has a good linearity.

A self-biased op-amp-free bandgap voltage reference circuit was designed in a 0.35 μm BCD technology to address the issues of input offset affecting voltage accuracy and poor power supply rejection in traditional references. It stabilized the output reference voltage through a negative feedback network, effectively eliminating the influence of the operational amplifier’s input offset voltage. By combining negative feedback and common-source/common-gate current mirrors, it enhances the reference’s immunity to interference, ensuring improved power supply rejection. The circuit utilized exponential curvature compensation for excellent temperature characteristics over a wide voltage range. Additionally, the self-biasing scheme minimized static current consumption. Simulation results demonstrate a 1.271 V output reference voltage at a 5 V supply, with a temperature coefficient of 5.46 ×10-6/℃ from -40 to 150 ℃, a -87 dB power supply rejection at DC, and a static current consumption of 2.3 μA. It is suitable for low power PM chips.

A new low power clock generator based on capacitor charging and discharging was designed in SMIC 0.18 μm CMOS process. In order to reduce the frequency fluctuation caused by temperature change, a negative temperature coefficient bias circuit was designed. The traditional duty cycle adjusting circuit was used to adjust the duty cycle of oscillation waveform. The simulation results show that the oscillator can stably output 7.16 MHz at 3.3 V supply voltage, and the system power consumption is 1.411 mW. The power consumption of the ring oscillator is 0.811 mW, and the phase noise is -104.4 dBc/Hz. In the temperature range of -40 ℃-110 ℃, the frequency of the oscillator changes from 7.116 MHz to 7.191 MHz, and the tolerance is within 1.05%. Compared with other clock generators, the circuit has the characteristics of simple structure, low power consumption, and high frequency stability in a wide temperature range. It can meet the working requirements of the chip and provide a stable clock for the chip.

A high precision RC oscillator with self-calibration based on frequency offset was proposed. The count offset between RC oscillator and reference clock was obtained by counting the PTAT high frequency ring oscillator. Further, the oscillator was stable by introducing a digital self-calibration circuit with the reduce of the count offset, which was derived from calibrating the reference voltage through a resistance array. The reference clock was only used on time during calibration and was not required in practical work. The proposed RC oscillator was fabricated in 0.18-μm CMOS process with a supply voltage of 1.8 V. The simulation results show that the circuit can generate a stable frequency of 2 MHz, and the power consumption of the entire system is 48.4 μW. The stable time is less than 15 μs. The frequency variation is less than ±0.2% in the temperature range of -40 ℃-125 ℃. The frequency variation is less than ±0.25%/V within the power supply voltage range of 1.70-1.98 V.

A high precision RC oscillator with chopper topology was designed in a 0.18 μm CMOS process. The structure had a better suppression effect on comparator’s offset, and compensated for the effect of comparator transmission delay on the output clock frequency to achieve better temperature characteristics. At the same time, the use of LDO power supply to the main circuit of the oscillator effectively suppressed the impact of power supply voltage fluctuations on the output frequency. In addition, the oscillator used a capacitive trimming network to reduce the impact of process drift on the center frequency. Simulation results show that the designed oscillator can be trimmed to calibrate the frequency to the nominal value of 2 MHz under different process corners. The fluctuation of the output frequency is only 0.87% in the temperature range of －40 to 125 ℃, and 0.21% in the power supply voltage range of 3 to 6 V. Compared with the same type of on-chip RC oscillator, the proposed circuit’s drift of temperature, supply voltage and process is better suppressed.

An ultra-wideband and high precision 6-bit phase shifter operating at 5-20 GHz was designed in SMIC 40 nm CMOS technology. The phase shifter was implemented through vector modulation and mainly consisted of input baluns, orthogonal signal generators, vector modulators, and digital to analog conversion circuits. For orthogonal signal generator, a three-stage poly-phase filter structure was designed to improve the bandwidth. A low error structure and current array control scheme were designed to reduce the phase error of the vector modulator. The post simulation results show that the input and output return loss are less than 8.85 dB and 10.12 dB respectively, the RMS phase error is less than 1.52°, and the RMS gain error is less than 0.17 dB. Under 2.5 V supply voltage, the power consumption is 43.50 mW. The chip size is 1.06 mm ×0.80 mm.

An ultra-wideband six-bit digital attenuator operating at frequencies ranging from 10.4 GHz to 28 GHz was designed and implemented in SMIC 40 nm CMOS process. The attenuator utilized an embedded switching-type structure, with the six-bit attenuation unit designed in three different topologies, T-type, bridge-T-type, and π-type. This six-bit attenuator achieves a step attenuation of 0.5 dB and a dynamic attenuation range of 31.5 dB. By incorporating a large attenuation amplitude compensation circuit and a cascaded structure of attenuation bits with excellent matching characteristics, the attenuator achieves a flat 64-state attenuation across the frequency range of 10.4 GHz to 28 GHz. The pre-simulation insertion loss of the attenuator ranges from 1.73 dB to 2.08 dB, while the post-simulation insertion loss ranges from 4.32 dB to 6.31 dB. Furthermore, the input and output return losses of all 64-states are less than -10 dB.

A novel low noise active inductor with mutually independent tuning of quality factor (Q) and inductance (L) was proposed, which was mainly composed of dual gyrators, modulation branch, adjustable feedback resistance, transconductance enhancement branch and noise suppression unit. Among them, the dual gyrators were formed by the first gyration loop and the second gyration loop in parallel to obtain large inductance values. The modulation branch could not only reduce the equivalent parallel resistance, and thus increase the Q value, but also achieve a wide tuning range of inductance value; The adjustable feedback resistor could not only increase the Q value, but also achieve independent adjustment of the Q value and compensate for the Q value’s changes resulted by tuning L value; The transconductance enhancement branch and the noise suppression unit reduced the noise of the first and second gyration loop, respectively, hence reduce the noise of the entire active inductor. By the deep cooperation not only among above circuit modules but also among the three configured external control terminal voltages, the excellent characteristics of Q and L values that coud be independently tuned each other and low noise were achieved. The simulation results show that the Q peak value can be adjusted from 674 to 5 083 with the regulation rate of as high as 153.2% at the frequency of 3.8 GHz, while the variation of inductance is only 0.3%. At 3.65 GHz, the L value can be adjusted from 6.1 nH to 15.5 nH with the tuning rate of as high as 87%, while the corresponding change of the Q value is only 3.7%. In the range of 2 GHz to 6 GHz, the maximum and minimum input noise of the actived inductor are 5.29 nV/Hz and 1.75 nV/Hz, respectively.

A novel low noise voltage controlled active inductor (VCAI) with simultaneously enhanced characteristics of Q-frequency was proposed. It mainly consisted of four modules, which was a dual feedback loop, a feed-forward branch, and two current mirrors. Among them, the dual feedback loop was used not only to form a gyrator to achieve inductance characteristics, but also to generate negative resistance to improve the Q value, and furthermore was configured with two voltage control terminals to adjust the inductance L value and Q value. And the two current mirrors were configured with two external voltage control terminals to provide DC bias and to further adjust L value and Q value. The feed-forward branch was connected to the positive transconductor of the gyrator to reduce the noise. Finally, both the cooperation of four modules and the joint regulation of the four control terminals made the VCAI not only achieve independent adjustment of the Q peak values relative to the L values at the same frequency, but also maintain the Q peak values basically unchanged at different frequencies, and also have low noise. The verification results indicate that at 3 GHz, the Q peak values can be significantly tuned from 135 to 1 132, while the L value only slightly changes from 43.50 nH to 43.89 nH. At 2 GHz, 3.4 GHz, and 5 GHz, the Q peak values are 682, 659, and 635, respectively, with a change rate of only 6.8%. At 1 GHz, the input reference noise voltage of VCAI is 3.2 nV/Hz, which is 6 nV/Hz lower than 9.2 nV/Hz for the AI without a feed-forward branch.

Sepic and Flyback topology were analyzed in this paper. To meet the requirements of DC/DC module power，auxiliary supply voltage was designed based on Sepic and Flyback mixed topology. The auxiliary supply voltage had multiple outputs and could realize the isolation of outputs. The model was derived by the state space averaging method. A closed loop control for Sepic converter was discussed in detail. The closed loop control had two control loops, voltage loop and current loop. Simulation were carried out to confirm the effectiveness of the topology by Matlab. The auxiliary supply voltage based on Sepic and Flyback mixed topology with three isolated 12 V and one non-isolated 6 V outputs was applied in a DC/DC converter that has wide input range and wide output range. Experimental verifications confirm the validity of the auxiliary supply voltage based on Sepic and Flyback mixed topology.

In recent years, with the development of automotive electronics and power drives, LDMOS with higher integration has received attention as a popular power device. How to increase its breakdown voltage and reduce its specific on-resistance has become the key to improve the device’s performance. Based on SOI LDMOS technology, a novel structure with a vertical field plate introduced in the SiO2 trench surrounded by a 4 μm high-K dielectric film was proposed in this paper. Compared with the traditional trench LDMOS, the vertical field plate and the high-K dielectric film fully guide the potential lines into the trench, which improves the breakdown voltage. In addition, the metal-insulator-semiconductor capacitive structure formed by the vertical field plate, the high-K dielectric and the drift region can increase the amount of charge on the surface of the drift region and reduce the specific on-resistance. Through 2-D simulation software, by introducing a vertical field plate with a width of 0.3 μm and a depth of 6.8 μm into a depth of 7.5 μm trench, an LDMOS was realized, with the breakdown voltage of 300 V, the specific on-resistance of 4.26 mΩ·cm2, and the Baliga quality factor of 21.14 MW·cm-2.

To optimize the trade-off relationship between EMI and Eonfor the floating P-base IGBT structure, a floating P-base IGBT structure with a dummy gate trench connected to a poly barrier layer was proposed. Two symmetrical dummy gate trenches were introduced in the floating P-base of the new structure, which were connected to each other by polysilicon. The dummy gate trenches divided the floating P-base into three parts, which decreased the number of holes accumulated near the gate trench and the inherent gate displacement current. The simulation results of the two-dimensional structure show that, compared with conventional IGBT, the proposed structure’s hole current density near the gate trench is reduces by 90% at low turn-on current. This reduction significantly reduces the peak values of collector current overshoot (ICE) and gate voltage overshoot (VGE), thereby improving the control capability of the gate resistance at dICE/dt and dVKA/dt. For the same turn-on loss, the maximum values of dICE/dt, dVCE/dt and dVKA/dt in the new structure are reduced by 32.22%, 38.41% and 12.92% respectively, thus reducing EMI noise and improving the trade-off between EMI noise and turn-on loss of the device.

To improve the breakdown voltage performance of silicon power devices and the flow direction of IGBT currents, a trench-field limiting ring composite termination structure was proposed. A floating polysilicon trench was introduced at the main junction, a trench with dielectric was introduced at the left side of the field limiting ring, and the right side of the trench was just intersected with the transverse expansion interface on the left side of the field limiting ring. The results show that this structure improves the distribution of IGBT main junction current wires, changes part of the current path to longitudinal flow, changes the collision ionization path, and improves the reliability of the device termination structure while increasing the main junction potential. The field limiting ring structure with dielectric slots further shortens the termination length, with a transverse to longitudinal depletion ratio of 3.79, which is reduced by 1.48% compared with that of the traditional field limiting ring structure. The utilization rate of silicon wafers is improved, thereby reducing the chip area and saving manufacturing costs. This method is very effective in the design of FLR termination.

The local discontinuous Galerkin (LDG) method has the advantages of high order of accuracy and efficiency of parallel implementation, and can work on many kinds of meshes. In this paper, the LDG method was adopted to solve the Laplace equation that governs the electric potential function for an integrated circuit layout, resulting in a new method to extract the capacitance of interconnects. The computational domain of this problem was derived by removing multiple conductor regions from a rectangular domain. For such special computational domains, it was numerically verified that the LDG method can achieve the theoretical convergence order. As the chip manufacturing process improves, the size and spacing of the conductors are getting smaller and smaller, which brings new difficulties to numerical simulations. In this paper, gradually coarsened meshes were used to significantly reduce the computational elements. The new method was applied to extract interconnect capacitance for seven circuit layouts that contain different numbers and shapes of conductors. The results are very close to the ones given by a commercial tool, indicating the effectiveness of the new method.

In order to improve the performance of capacitive MEMS microwave power chip, a novel high performance MEMS microwave power chip was designed. By establishing a dual-guided clamped beam capacitance model, the transmission characteristics, overload power and sensitivity characteristics of the sensor were analyzed. Two equivalent conditions were proposed for the parallel plates in the dual-guided clamped beam capacitance model. At the same time, a new beam width equivalent method was proposed to solve the mismatch problem of the equivalent beam width of the dual-guided structure, reducing the relative error of the model. The dual-guided clamped beam capacitance model explained the impact of the thickness to length ratio and initial height of the guide beam on the overload power and sensitivity of the sensor. The test results show that the sensitivity of the dual-guided clamped beam MEMS microwave power sensor is 14.3 fF/W within 200 mW input power, while the theoretical value of sensitivity is 13.5 fF/W with a relative error of only 5.6%. Therefore, this theoretical model has certain reference significance for the design of clamped beam MEMS microwave power sensors.

A 1 200 V/20 A SiC MPS with hexagonal cell realizing low leakage current and high surge current was fabricated through implantation optimization. Under 25 ℃ and 175 ℃ test condition, the results show that its on-state voltage drop (VF) is 1.48 V and 2.03 V, respectively. Owing to optimized implantation and layout design, the maximum electric field at the Schottky contact is only 1.25 MV/cm at 1 200 V. Correspondingly, the leakage current of the device @1 200 V is only 4.3 μA (@25 ℃) and 13.7 μA (@175 ℃), respectively. Moreover, its surge current capability at 25 ℃ and 150 ℃ reaches 258 A and 252 A, which is about 13 times of the rated current.

Mg-doped NiO (Ni0.61Mg0.39O) thin films were fabricated by using magnetron sputtering "co-sputtering" method. Ar gas was used as the sputtering gas, high-purity NiO and MgO double ceramic targets were used as the sputtering target. The sputtering power of NiO and MgO target was controlled at 190 W and 580 W respectively, the sputtering vacuum degree was kept 2 Pa, and the substrate temperature was kept at 300 ℃. The obtained thin film was a crystalline film with (200) preferred orientation. The surface was relatively flat and the distribution of the grains was dense. The grain size of the film was about 46.9 nm, and the diffraction peak position of (200) was shifted to small angle of about 0.2° compared with that of the undoped NiO film. The film had a high transmittance in the visible light region, but the transmittance dropped sharply near 300 nm. The optical bandgap of the film moved to 3.95 eV towards higher energy direction. It provides technical support for the fabrication of high quality Mg-doped NiO thin films using magnetron sputtering co-sputtering method.

The critical path exhibits significant variations under different process corners, necessitating extensive static timing analysis. Consequently, timing analysis needs long execution times, and the accuracy of static timing analysis becomes increasingly important as process sizes continue to shrink. A machine learning-based delay prediction method specifically designed for different process corners was proposed in this paper. By considering the impact of Process, Voltage and Temperature (PVT) on timing, the critical path was globally aggregated and encoded by using a self-attention transformer model to predict the statistical delay across various PVT conditions. The verifications using the EPFL reference circuit demonstrate that the average absolute error of the proposed method ranges from 5.8% to 9.4%, showcasing its strong prediction performance. This approach can enhance the accuracy and efficiency of timing analysis, leading to shorter design cycles and reduced costs in digital circuit design.

With the wide application of FPGA in the fields such as commercial or national defense, the security of FPGA is facing great challenges and many attacks against FPGA have been proposed. In order to further research the security mechanism of the FPGA, this paper introduced a new Side-Channel Analysis (SCA) method and firstly studied the security vulnerabilities of bitstream encryption in the loading process of Xilinx Virtex-7 chips. Compared with previous targets, Virtex-7 chips have larger chip scale, lower signal-to-noise ratio, and are more difficult to be attacked. Previous studies always use SASEBO or SAKURA boards that are specially designed for SCA, while this study is the first to be carried out on Xilinx official evaluation board. The board does not consider the side-channel measurement acquisition case, so some manually modification is needed and then an adequate signal-to-noise ratio can be obtained. The Electro Magnetic (EM) radiation was took as the side-channel measurement, and each set key can be obtained within 800,000 EM traces. The adversary can obtain the bitstream plaintext by using the key, and then reverse the FPGA design or clone products, and so on. It will affect the security of FPGA.

With the development of wafer process nodes, the package integration is increasingly higher. As a result, the linewidth and spacing of the packaged organic substrate gradually decrease, the number of micropore increases, and its pore diameter decreases. The micropore failure of organic substrate in ball grid array (BGA) packaging has always been a major problem affecting the reliability of high performance and high density chip packaging. Aiming at the micropore failure in organic substrate, the failure modes of flip welding under 500 times of temperature cycle loading at -65 ℃ - 150 ℃ and -55 ℃ - 125 ℃ were studied systematically by means of temperature cycle reliability test, finite element analysis, focused ion beam, scanning electron microscope and energy spectrometer. The results show that the micropores of organic substrates are delaminated due to temperature cyclic fatigue stress under the condition of temperature cycle from-65 ℃ to 150 ℃. The simulation results show that the average equivalent stress of the substrate increases by about 8 MPa. Subsequently, the structure of the heat dissipation cover is improved. After the improvement, the equivalent stress is reduced by 21.4%, and it can pass the reliability verification of 500 times thermal cycling from -65 ℃ to 150 ℃, which meets the requirements of high reliability.