Design and implement a ultra-high-speed data acquisition and analysis platform, consisting of FPGA data acquisition excitation boards, test analysis software, and PCs. This system is used for the testing and analysis of analog-to-digital converters (ADC) and digital-to-analog converters (DAC) using the JESD204C interface protocol. The platform is constructed from three aspects: component selection, PCB design and simulation,excitation, and software testing to ensure stable operation of the platform at the transmission rate of the JESD204C protocol. Based on this platform, dynamic performance tests were conducted on a 6 GSPS dual-channel 16 bit ADC and a 12 GSPS four-channel 16 bit DAC chip. The test results show that the SNR of the ADC is 56.3 dBFS, and the SFDR of the DAC is 65.5 dBFS, with performance indicators close to the manual values, indicating that the functionality and performance of the data acquisition platform have been verified and can be extended to testing other chips using the JESD204C interface protocol, demonstrating a certain degree of versatility.