A multi-stage noise-shaping (MASH) structure interstage op-amp sharing Σ-Δ modulator was designed in a 55 nm CMOS process. A 2-2 MASH structure was used to design the modulator parameters. An improvement had been made to the classical switched-capacitor integrator and applied to the design of the modulator circuit, realizing the sharing of op-amps between the two stages of the modulator, reducing the number of op-amps while achieving high precision, and significantly decreasing the power consumption of the MASH structure modulator. Simulation results show that at a supply voltage of 3.3 V, the modulator have a signal-to-noise-and-distortion ratio of 111.7 dB, a spurious-free dynamic range of 113.6 dB, and a total power consumption of 16.84 mW.