The local discontinuous Galerkin (LDG) method has the advantages of high order of accuracy and efficiency of parallel implementation, and can work on many kinds of meshes. In this paper, the LDG method was adopted to solve the Laplace equation that governs the electric potential function for an integrated circuit layout, resulting in a new method to extract the capacitance of interconnects. The computational domain of this problem was derived by removing multiple conductor regions from a rectangular domain. For such special computational domains, it was numerically verified that the LDG method can achieve the theoretical convergence order. As the chip manufacturing process improves, the size and spacing of the conductors are getting smaller and smaller, which brings new difficulties to numerical simulations. In this paper, gradually coarsened meshes were used to significantly reduce the computational elements. The new method was applied to extract interconnect capacitance for seven circuit layouts that contain different numbers and shapes of conductors. The results are very close to the ones given by a commercial tool, indicating the effectiveness of the new method.