An ultra-wideband sampling/holding circuit was designed in a 013 μm SiGe BJT process. The auxiliary switching circuit was used to process the signal in advance, which improved the linearity of the circuit. The fully differential open loop structure and multi-stage cascade output buffer were adopted to reduce the sagging rate effectively. The simulation was performed by Cadence Spectre at 5 V supply voltage and 100 fF load capacitance. The results showed that the clock frequency was 4 GHz under coherent sampling. At high frequency of 18 GHz, the SFDR reached 6399 dB, so the high frequency characteristics was good. The bandwidth of the circuit was up to 251 GHz. It was suitable for high speed A/D converters.