A symmetrical square enclosed layout transistor (SS-ELT) NMOS device structure was introduced. Equivalent aspect ratio W/L model and total ionizing dose (TID) radiation-hard performance of the SS-ELT NMOS were also studied. Based on regional decomposition and conformal mapping, et al., the model of equivalent aspect ratio W/L was derived. The chips were fabricated in a 018 μm BCD process. Both standard NMOS and SS-ELT NMOS with different sizes were tested under irradiated environment and non-irradiated environment. The tested results showed that the percentage error of equivalent aspect ratio W/L model of the SS-ELT NMOS could be as low as 5%. Under the condition of 10 kGy TID, the off-state leakage current of the SS-ELT NMOS could still be maintained at a very low level, which reflected its great TID tolerance.