Based on a 0.13 μm SiGe BiCMOS process, a linear driver was designed. With the advantages of high speed and large swing, the driver supported to linearly drive Traveling-Wave Mach-Zehnder Modulator (TW-MZM) to meet the application requirements of 100 Gbit/s single channel in optical communication systems. The driver included Continuous Time Linear Equalization (CTLE), Variable Gain Amplifier (VGA) and the output stage optimized based on cascode structure. It achieved adjustable gain and avoided transistor breakdown caused by large output swing. Simulation results show that the -3 dB bandwidth of the driver is 43 GHz, and its gain is adjustable from 15 dB to 25 dB. Under 56 Gbaud NRZ/PAM4 signal input, eye diagrams are measured well. The differential output swing pp value is up to 4 V, the total power consumption of the driver is 1.02 W, and the occupied area is 0.33 mm2.

In order to meet the application requirement of passive RFID, a low power CMOS temperature sensor was designed in SMIC 0.18 μm CMOS process. The sensor firstly converted the temperature signal into a voltage one through double-transistor circuits and then into a current signal. Afterwards, the signal was converted into a frequency one by a ring oscillating circuit. Eventually the signal was output in the form of a binary number by a counter circuit. Simulation results demonstrate that the sensor achieves good linearity and accuracy in the range of -20-100 ℃, and only consumes power of 1.05 μW, which can be potentially applied in the field of RFID.

An ultra-low power fast transient response NMOS LDO with adaptive charge pump was designed. The whole circuit mainly included an error amplifier module, a buffer module, a power stage, a dynamic zero module and an adaptive charge pump module. The adaptive charge pump could adjust the operating frequency according to the size of the load current. It ensured the ultra-low power consumption under light load conditions while taking into account the requirements of the gate of the power transistor under heavy load conditions. At the same time, in order to meet the needs of fast transient response in the circuit, a dynamic current circuit was added. The circuit was designed in a BCD 0.18 μm process. Its working voltage range is 2.5-3.6 V, the output voltage is 1.2 V, the load range is 10 μA-20 mA, and the working temperature range is -40-125 ℃. The simulation results show that the designed LDO power supply voltage regulation rate can reach 1.123 mV/V, the recovery time of heavy load jumping to light load and the recovery time of light load jumping to heavy load are 260 μs and 5 μs respectively, while the minimum quiescent current is only 0.291 μA.

A low power and low reference spur charge pump PLL with high matching charge pump and precision automatic frequency calibration circuit was designed. It consisted of D-trigger PFD, 5 bit digital programmable frequency modulation LC VCO, 16-400 programmable frequency divider and automatic frequency calibration (AFC) circuit. An improved charge pump circuit was designed to reduce the current mismatch of the high matching charge pump by increasing the output impedance of the current mirror. By adopting the frequency band preselection fast search method, the AFC circuit locked the frequency accurately with lower voltage gain of LC VCO, extended the range of locked frequency, and kept the output reference spurs lower enough. The PLL was designed in a 40 nm CMOS process with 1.1 V power supply. The simulation results show that the charge pump matched voltage range is 0.19-0.88 V, the oscillation frequency range is 5.9-6.4 GHz, the power is less than 6.5 mW@6 GHz, and the maximum current mismatch is less than 0.2%@75 μA. When the signal frequency is 6 GHz, the output phase noise is -113.3 dBc/Hz@1 MHz, and the reference spur is -62.3 dBc.

A floating voltage driver circuit was designed for fully integrated switched capacitor power converter (SCPC). The interleaved bootstrap control technique was used, which periodically utilized certain cells in the multiphase interleaved SCPC to provide bootstrap drive for other cells. The floating voltage drive for all power switches was implemented and was suitable for all SCPC topologies. Compared with the traditional scheme, the hardware overhead of the proposed floating voltage driving circuit was independent with the number of devices in the SCPC. It was applied in an 8-phase reconfigurable SCPC, and the simulation results proved the correctness of this design.

A 4×112 Git/s high speed PAM-4 transimpedance amplifier was designed in a 90 nm SiGe BiCMOS IC process. A shunt-feedback input stage was used to realize high bandwidth and low noise performance. A novel double Gilbert cell based variable gain amplifier was creatively proposed to accommodate input current with a wide dynamic range. The emitter degeneration technique was used to boost the bandwidth and improve the linearity of the circuit. The chip measurement results show that the optical receiver front-end can achieve a maximum transimpedance gain of 74 dBΩ, a bandwidth of 32 GHz, an input-referred noise current density of 5.6 pA·Hz-1/2, and a less than 5% total harmonic distortion with up to 3 mA input current. The transimpedance amplifier was further integrated into a 400G QSFP-DD optical module. The measurement results show that the module performance satisfies the sensitivity and transmission distance requirements of IEEE 400G Ethernet FR4 standard.

In the half-bridge gate driver, the low voltage domain PWM signal needs to be converted into a high-side floating voltage domain PWM signal through a level shifter, thereby turning on or off the high-side power transistor. The fast floating of the floating power rail will cause dV/dt noise, which affects the reliability of the signal transmission of the level shifter. In this paper, the auxiliary circuits were designed to prevent false turn-on and turn-off respectively in the level shifter. When the upper bridge arm turned on, once detecting dV/dt noise, the auxiliary circuit for preventing false shutdown could keep the output of the level shifter in a high level state to prevent the upper bridge arm from being turned off by mistake. When the upper bridge arm turned off, once detecting dV/dt noise, the auxiliary circuit for preventing false turn-on could keep the output of the level shifter in a low level state to prevent the upper bridge arm from being turned on by mistake. Based on 0.18 μm BCD process simulation verification, the designed level shifter has only 1.2 ns turn-on transmission delay, and 100 V/ns dV/dt slewing immunity.

A kind of bandgap reference circuit without operational amplifier was designed. By using the voltage self-adjusting technology to stabilize output reference voltage, the PSRR of the proposed bandgap reference circuit was raised. At the same time, due to without the operational amplifier, the circuit avoided the effect for output voltage caused by op-amp offset voltage, which improved the temperature coefficient of the reference, and reduced the complexity of the circuit. Based on a 0.18 μm BCD process, the PSRR of the circuit is -94 dB at 10 Hz and -44 dB at 1 MHz by simulation under Cadence environment. And the temperature coefficient is 4×10-6/℃ in the temperature range of -40-+125 ℃. Including the start-up circuit, the static current of the bandgap reference circuit is about 14 μA, and the on-chip area is about 0.016 mm2.

In order to meet the design requirement of front-end readout circuit for radiation detectors, a fully on-chip fast transient response LDO was designed in a 0.18 μm standard CMOS process. A large output swing high gain amplifier was utilized to drive the pass transistor, which could increase the gate voltage swing of the pass transistor. Thus, the dimension of the pass transistor and the dropout voltage were reduced. The loop-gain of LDO and the charge/discharge gate current of the pass transistor were increased, which is helpful for improving the transient response. In order to keep LDO stable under all load current conditions without sacrificing the loop-gain bandwidth and the die area, a frequency compensation method based on load current partition was proposed. The simulation results demonstrate that the phase margin is greater than 53° at the load capacitance of 200 nF and the load current ranging from 0 to 200 mA. With the help of large output swing and high gain amplifier, the maximum output current can be increased by two times when the dimension of pass transistor is the same. The settling time is smaller than 6.5 μs when the load current suddenly increases from 10 mA to 200 mA. The die area of the proposed LDO is 120 μm×264 μm. The power efficiency at full load is 97.76% and the minimum dropout voltage is 50 mV.

A reflection-type tunable analog phase shifter applied to phased array system for S-band satellite communication was designed. The phase shifter expanded the bandwidth and improved the standing wave in the working frequency band by using a three-branch directional coupler. The L-shaped reflection load composed of a transmission line and a varactor diode enlarged the phase shift. The measurement results show that the phase shift reach 191°±1° in the uplink frequency band from 1.98 GHz to 2.01 GHz, and 186°±0.1° in the downlink frequency band from 2.17 GHz to 2.2 GHz. The insertion loss is better than 3.3 dB, and the fluctuation of insertion loss is less than 1 dB. The return loss is greater than 20 dB in the whole voltage tuning range. The proposed phased shifter is simple in structure, easy to tune and low in price, and had certain application value in the field of satellite communication.

Based on the EPC class-1 generation-2 protocol, the system specifications of the frequency synthesizer working in the global UHF RFID band was analyzed. By using the standard 0.18 μm CMOS process and integrating a new adaptive frequency calibration module, a low phase noise, fast locking fractional frequency synthesizer was designed. The LC-VCO was based on the tailless current source topology and utilized the second harmonic filtering technology to significantly reduce the phase noise in band. In addition, the adaptive frequency calibration circuit was different from the traditional binary comparison method. It was based on a novel successive comparison method to reduce the comparison time of the 4-bit digital logical control voltage of the VCO. Therefore, the control words of the VCO could be quickly determined and the locking time could be improved. The simulation results show that the locking time is only 6.3 μs during the adaptive calibration period, the overall locking time of the loop is lower than 23.2 μs, its phase noise performance is -106.3 dBc/Hz at 100 kHz frequency offset and -126.1 dBc/Hz at 1 MHz frequency offset, and the overall power consumption is 84 mW. Compared with the performance of the recently released advanced CMOS fractional-N frequency synthesizer, the proposed one achieves considerable phase noise performance, and works with shorter locking time and lower power consumption.

Aiming at the urgent needs of low 3rd order intermodulation distortion RF amplifiers in wideband large signal capacity wireless systems, this paper presents the optimization design methods of HBT based low 3rd order intermodulation distortion RF amplifiers from two aspects: amplifier bias point optimization and on-chip thermal optimization. The relationship between intermodulation and DC bias condition of Darlington configured RF amplifier was investigated. The DC bias point for optimum 3rd order intercept point (IP3) was obtained. An on-chip heat dissipation optimization circuit structure and a distributed layout were proposed to further improve the IP3. Based on the proposed optimization scheme, a 0.05-1 GHz RF amplifier with low intermodulation was designed in a 2 μm AlGaAs/GaAs HBT process. The tested results show that the amplifier exhibits an output IP3 of 42.1 dBm. The point ratio of IP3-1 dB compression reaches 21.2 dB.

A low cost 2 kbit EEPROM memory was designed in a 350 nm 2-poly 3-metal EEPROM process for low frequency passive RFID applications. The design minimized the layout area by optimizing the Dickson charge pump and the readout circuit, while ensuring that the memory capacity could meet most usage scenarios. The optimized Dickson charge pump provided a stable voltage boost from 3.3 V to 16 V in 10 μs with the power consumption of 334 μW. The readout circuit was based on detecting the threshold voltage of the NCG device to discriminate the stored logic value, which eliminated the need for a high precision current reference circuit and a sensitive amplifier with high gain, effectively reducing the overall circuit area. The low cost 2 kbit EEPROM operated at 3.3 V and was capable of 32 bit parallel input and one-bit serial output, with a total chip area of 0.14 mm2, effectively reducing the complexity and manufacturing cost of low frequency passive RFID designs.

A wide-band low jitter phase-locked loop applied to HDMI receiver circuit was designed in a 110 nm CMOS technology. The circuit used an improved charge pump with double loop structure to realize fast locking in a wide input frequency range of 25 ~ 250 MHz, and a clock signal with a tuning range of 125 MHz~ 1.25 GHz was generated through a pseudo differential ring oscillator with high phase noise performance. The simulation results show that the locking time of the PLL is less than 1.2 μs. When the operating frequency of the oscillator is 0.8 GHz, the phase noise is -100.0 dBc/Hz @ 1 MHz, and the peak to peak jitter of the output clock is 4.49 ps.

The latest research progress and mass production of SiGe BiCMOS technology in recent years have been reviewed. The device structure, process flow and performance reported by different institution are presented and discussed in detail. Moreover, the direction of further optimization of device and process is prospected. Although traditional DPSA-SEG architecture has achieved the best mass production performance, it is difficult to further improve its device performance due to the high base link resistance and the inhomogeneity of selective epitaxial base film. NSEG has achieved very high performance in the laboratory, but its low self-alignment degrees hinder industrial mass production and larger-scale integration. It is becoming more and more difficult to maintain the process compatibility of HBT devices with smaller baseline CMOS. It remains a difficult challenge to work out solutions that combine high performance, mass production, and low cost.

With Moore's law approaching the limit, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a powerful substitute for CMOS transistors below 5 nm. The CNTFET has a quasi one-dimensional structure, and the gate can effectively control the on/off of the conductive channel. At the same time, the carrier can realize ballistic transport in the channel, and has a very high mobility. Therefore, CNTFET can provide large current transmission capacity in low voltage environment, which provides a solution for the implementation of nano scale ultra large-scale analog/logic circuits. This paper summarizes the development status of CNTFET compact model, analyzes the problems faced at this stage, such as accurate drain current model, tunneling effect, parasitic effect and multi-nanotube model, and focuses on the solutions to the above problems. At the end, the future application prospect of the compact model is discussed.

Wearable devices, which are widely used, require stretchable and bendable sensors, so flexible sensors have received much attention. This paper presents a review of flexible pressure sensors in terms of microstructures, materials, and preparation processes, focusing on summarizing the different structures of flexible sensors at the present stage and comparing the important properties of flexible pressure sensors with natural microstructures, bionic surface microstructures, porous structures, multilevel structures, and multilayer structures. The commonly used flexible substrate materials and conductive active materials are introduced. Comparing the advantages and disadvantages of lithography technology, 3D printing and other manufacturing processes, it is found that the flexible pressure sensor with excellent comprehensive performance and repeatability is more complicated to manufacture and has a higher cost. The future research direction of flexible pressure sensor is prospected. This paper has a high theoretical value and engineering reference significance for related flexible devices.

In order to improve the sensitivity characteristics of the on-line MEMS microwave power sensors, a novel type of MEMS microwave power sensor with double cantilever beams was designed. The measured electrodes and the anchors were located on opposite sides of the central signal line in this structure. A lumped equivalent model of double cantilever beam circuit was established, and the microwave characteristics of the double cantilever beam were studied. A pivot-type static model of double cantilever beam was established. The overload power and the sensitivity of this novel cantilever beam structure were theoretically analyzed. The results show that the sensitivity of the novel double cantilever beam structure is 6-8 times higher than that of the traditional single cantilever structure in which the measured electrode and the anchor are located on the same side of the signal line. It solves the disadvantage of the low sensitivity of the capacitive microwave power sensor to a certain extent.

In order to improve the performance of laser-induced graphene pressure sensors under the premise of low cost and easy preparation, an amplification structure of graphene pressure sensor was designed. The surface structure of laser-induced graphene pressure sensor was characterized, and the influence of the surface porous foam structure on the piezoresistive effect was analyzed. COMSOL software was used to simulate and analyze the stress of the sensor amplification structure, and the stress of graphene layer under external pressure was obtained. The amplification substrate was 3D printed with the resin material, which took into account the properties of light weight, high precision, and high mechanical strength at low cost. The tested results show that when the pressure is in the range of 5-20 kPa, the sensitivity of the amplified structure is increased by about 43% compared with that of the non-amplified structure.

Two-dimensional semiconductor materials represented by MoS2 are one of the next-generation potential electronic materials that continue Moore's Law. However, the two-dimensional nature makes the transport behavior of electrons in MoS2 highly sensitive to environmental conditions. Encapsulation with van der Waals insulator materials is one of the effective solutions to eliminate the environmental sensitivity of two-dimentional semiconductor devices. In this paper, a novel van der Waals insulator material CrOCl was prepared by chemical vapor transport (CVT), and MoS2-based field effect transistors were designed and fabricated by using few-layer CrOCl as the dielectric layer and encapsulation material. The room temperature field effect mobility of MoS2 transistor with CrOCl as bottom gate dielectric layer and encapsulation material is about 60 cm2·V-1·s-1, which further increases to 100 cm2·V-1·s-1 at 2 K. In addition, compared with the hysteresis window of 20 V for unencapsulated MoS2 transistors, the protection of CrOCl effectively eliminates the hysteresis phenomenon of transistor transfer characteristics, proving its application potential in 2D material electronics.

In order to meet the ESD protection requirements of small size devices, a STI double-fin structure with parasitic SCR based on fin technology is proposed. By adopting double-fin layout and deep doping technology, the base region width of the device was reduced, which avoided the SCR failure caused by weak conductivity modulation in fin technology. The simulation results show that compared with DFSD structure, the It2/Wlayout of the new structure is increased from 21.67 mA/μm to 28.33 mA/μm, and the trigger voltage Vt1 is decreased from 14.08 V to 9.64 V. The new structure can be turned on effectively and discharge large current under ESD stress.

At present, there is a wide demand for single-pole multi-throw switch in communication, navigation and other fields. However, this kind of switch is usually large in size, narrow in working frequency band, large in insertion loss and low in isolation. A series-contact double-sided multi-contact RF MEMS single pole six throw switch was designed to solve the above problems in this paper. Three circular contacts were placed on the lower electrode of the switch, and the distal end was connected with a horn shaped transition belt. Above it were "X" shaped upper electrodes with slot. This structure could improve RF performance greatly by reducing coupling capacitance and contact resistance. HFSS software was used to simulate and optimize the switch. Its operating frequency can cover L~Ka band. At 26.5 GHz, the insertion loss is less than or equal to 0.3 dB, and the isolation degree is more than or equal to 37 dB. In addition, its size is 1.05×1.05×0.5 mm3.The results show that the proposed single pole six throw switch has great RF performance and meets the requirements of miniaturization. Therefore, it has a large application prospect in L~Ka band navigation, cognitive radio network and microwave testing.

The avalanche multiplication effect is the key mechanism of 4H-SiC avalanche photodiodes and power semiconductor devices. As the most important physical parameter, the accurate analytical expression of avalanche multiplication factor (M) has not been reported. In this article, an analytical empirical formula of multiplication factor for 4H-SiC p-n junction was presented based on accurate theoretical methodology. Utilizing the accurate impact ionization model, the impact ionization integrals (I) of electron and hole for a 4H-SiC abrupt diode were calculated by MATLAB. The simulations were carried out by MEDICI to verify the theoretical results. Breakdown voltage (BV) as a function of doping concentration was established. Ulteriorly, the multiplication factor as a function of doping concentration and reversely-biased voltage was derived in an empirical form. The research on the relative error analysis on I indicates that a tiny relative error of the electric field could lead to a large relative error of I. For a wide range of BV, the empirical formula could achieve a high accuracy for VR larger than 0.65BV with relative error less than 5%.

The variety of fin structure induced by process variation can make the nano FinFET device present different electrical properties. This fact complicates their single event transient (SET) effects. Based on the calibrated standard SOI FinFET device at 14 nm technology node, five structures, including the types of bullet, triangle, stepped, semicircular and bottom elliptic, were built up in this paper. The correlation relationship between the characterization of SET and the parameters of the fin structure was analyzed. Their relevancies were obtained by the grey theory. The results show that the collection charge and deposited charge are significantly associated with the cross section area of fin. The peak value of SET current, peak value of electron-hole pairs generation rate and bipolar amplification coefficient, not only depend on the cross section area of fin, but also depend on the effective channel width. Their dependences on the effective channel width are more remarkable.

Based on traditional common source - common gate - common drain (CS-CG-CD) active inductors (AI), an improved AI is proposed. Firstly, both the first feedback loop with parallel resistance and the second feedback loop with small size transistor were introduced between CG transistor of the negative transconductor and CD transistor of the positive transconductor. Secondly, the tuning branch circuit was introduced between CS transistor of the negative transconductor and CD transistor of the positive transconductor. Furthermore, the cooperation among above different modules and the joint adjustment of their external tuning terminal voltages realized two reconfigurable performances as follows: 1) high Q peak values could be achieved and tuned independently relative to the inductance values in a large range at the same frequency; 2) high Q peak values could be obtained and kept almost unchanged at different frequencies. The verification results show that at the frequency of 5.81 GHz, the Q peak value can be adjusted from 1 132 to 15 491 with the tuning percentage of 1 268.5%. Meanwhile, the inductance values change from 7.65 nH to 7.67 nH with the variation of only 0.26%. Under the frequencies of 5.72 GHz, 7.12 GHz and 7.93 GHz, the Q peak values can be high up to 1 274, 1 317 and 1 310 respectively, and the variation percentage is only 3.38%. Meanwhile, the large inductance values of 7.62 nH, 8.08 nH and 8.81 nH can be obtained respectively. It consumes about 38.61 mW.

An L-band multilayer low group delay filter is proposed to solve the problems of large volume, high group delay and large loss of current L-band filters. By selecting high silicon base as substrate material, a multilayer interfingering structure resonator was adopted to reduce in-band group delay and volume. HFSS software was used to implement modeling and simulating of the proposed filter. By adjusting the parameters of the resonator, the optimal design scheme was obtained. Simulation results show that the center frequency of the filter is 1.5 GHz, the in-band insertion loss is less than 1.2 dB, the in-band group delay fluctuation is less than 500 ps, and the out-of-band suppression at the center frequency around 0.3 GHz reaches 50 dB with a small size of 8 mm×7 mm×1.5 mm.

The bonding strength decay law of three kinds of gold wire of 18, 25, 30 μm, and aluminum wire of 25, 32, 45 μm under different temperature cycles, as well as the ratio of the breaking mode were studied. The results show that, all test samples, regardless of whether they undergo temperature cycles, have reached the minimum bond strength requirement of GJB548B-2005, and there is no puff-off mode. As the times of temperature cycles increase, the bonding strength of the gold wire increases slightly at first, then slowly decreases and tends to level off. Meanwhile, the bonding strength of aluminum wire decreases rapidly first, then decreases slowly, and tends to be gentle. Compared with gold wire, the bonding strength of aluminum wire decays faster under temperature cycles of 0 to 50 times. The article also obtains the bond strength attenuation change equation under different wire diameters through curve fitting.