A Triple-RESURF LDMOS (TR LDMOS) with segmented P buried layer (SETR LDMOS) is proposed. This structure cut the uniformly doped P buried layer of drain side in the traditional TR LDMOS, and the P-type impurities in the drift region presented a nearly stepped doping distribution from the source to the drain side. This optimization could balance the severe substrate-assisted depletion effect at the bottom of the drain terminal, and improve the breakdown voltage of the device. At the same time, when the device turned on, current transmission path was not obstructed, maintaining a low specific on-resistance. The tape-out results show that the breakdown voltage of SETR LDMOS can reach 813 V with the same drift region length of 65 μm. Compared with TR LDMOS, the breakdown voltage of SETR LDMOS is increased by 51 V, with the same specific on-resistance of 7.3 Ω·mm2.