In order to meet the sampling requirements of serial transceiver data with different rates, a wideband low jitter PLL clock was designed based on the reconfigurable charge pump array. To realize low jitter clock output with wide frequency range, the output current of the charge pump array was adaptively matched according to the PLL frequency-multiplier factor. The PLL was designed in a 40 nm CMOS process, and the area was 367*569 μm2. The experimental results show that the tuning range of the PLL is 1~4 GHz, the clock output RMS jitter is 3.01 ps@1.25 GHz and 3.98 ps@4 GHz, and the peak-peak jitter is less than 0.1UI.