A low power SRAM architecture for error-tolerant applications is proposed. By pre-coding the input data, the proposed SRAM architecture reduced the power consumption of SRAM circuit with acceptable loss of precision. A single-ended 8T (SE-8T) SRAM bit cell was designed. The proposed SE-8T cell improve read stability by the using of a read buffer. The write ability of SE-8T was improved by breaking the feedback loop of the cell. Cooperated with the SE-8T, the approximate SRAM worked well under ultra-low supply voltage. The proposed SRAM circuit was simulated in the 40-nm standard CMOS technology. The simulation results show that the stability of SE-8T is high while the power consumption is low. Therefore, the power consumption of the proposed SE-8T based approximate SRAM is very low. At 0.5 V supply voltage, the power consumption of proposed approximate SRAM is 59.86% less than that of conventional 6T under the same operation frequency.