A two-stage cascaded broadband low noise amplifier(LNA)chip with working frequency of 2.0-4.2 GHz was fabricated in Sanan's 0.25 μm E-Mode pHEMT process through ADS simulation software. The chip realized 3.3 V single power supply with resistance bias voltage. At the same time, an improved RLC parallel negative feedback structure was designed to realize broadband matching. The simulation results show that the maximum gain of the LNA is 30.9 dB, and the gain flatness is about ± 0.6 dB. The return loss of input is less than -9 dB, and the return loss of output is less than -12 dB. The noise figure is (1.2±0.14) dB in the frequency band of 2.0-4.2 GHz. The system stability factor K is greater than 2.8 in the whole frequency band, and the area of the chip is 0.78 mm×2.2 mm.