An adaptive dead time control circuit for GaN gate driver is proposed, with low time delay, low power, high speed, and high switching frequency. The switching node voltage was detected by a single-pulse generation circuit to achieve zero static power dissipation. An interlocking circuit was designed to avoid false triggering which may lead to a shoot-through state. The proposed circuit was designed in SMIC 0.18 μm BCD process. The simulation results show that the dead time is adaptively adjusted along with the load. When the dv/dt of switching node voltage is 48 V/ns, which is the worst working condition, the dead time error of the high and low side are only 1.59 ns and 2.69 ns respectively.