A high-speed asynchronous FIFO chip was designed in a 0.18 μm CMOS technology for 100 Gbit/s Ethernet PCS link system. Dual-port 8-transistor architecture instead of register in the memory cell was employed to increase transmission rate. Sense amplifier adopted latch-base amplifier combined with pre-charge technology to amplify the tiny signal between bitlines in reading phase for the smaller transmission latency. In order to reduce the writing time and the reading time, the effect of transistor size on the level flip time was also analyzed and simulated in detail, which not only met the requirement of rate, but also obtained the high reliability signal. The whole chip area including pads was 1.43 mm2. Test results show that the FIFO can operate over 1.05 GHz and the eye diagram of the output signal is clear with the horizontal opening degree reaching 0.91UI. The total power consumption is 143.3 mW at the supply voltage of 1.8 V. The designed FIFO is more suitable for 16×6.25 Gbit/s PCS link system.