A low noise high PSR low dropout voltage (LDO) was designed in a 28 nm CMOS process. A folded cascode structure was adopted to design the high output impedance and high-gain error amplifier, which reduced the effect of power supply noise on the output. A cascode Miller compensation structure was used to ensure a high phase margin under both light and heavy load, enhancing the LDO loop stability. A noise reduction module was applied to the input of error amplifier, which reduced the impact of noise on the whole LDO circuit. The simulation and analysis with Cadence Spectre show that, under 1.9 V power supply voltage and the load varied from 10 mA to 60 mA, the loop gain is 77.6~91 dB, and the phase margin reaches 76°~79°. The power supply rejection (PSR) and noise were simulated under intermediate load current of 30 mA. The results show that the power supply rejection is -81.9 dB and the low frequency noise (1 kHz) is 258 nV· HZ-1/2. The layout design and post-imitation comparison of the whole LDO circuit were carried out. The results show that the loop gain is 83.2 dB, the phase margin is 78°, the PSR is -78.3 dB, and the low-frequency noise (1 kHz) is 283 nV· HZ-1/2.