The method of nested Miller compensation using dual zero-regulator resistors was proposed, and a large-capacitance drive amplifier with a high-gain feed-forward transconductance stage was designed. The amplifier achieved high gain-bandwidth product and large phase-angle margin without requiring stringent passive compensation component matching requirements, thus enhancing the design system's immunity to process, voltage, and temperature variations. The proposed amplifier had a simple topology and it could be applied to amplifiers with rail-to-rail input and output. A design example of a three-stage rail-to-rail class AB amplifier was presented based on 0.35 μm CMOS process, and the performance of the amplifier was tested. The test results show that under the condition of 200 kΩ resistive load and 600 pF capacitive load in parallel, the gain bandwidth product is 4.4 MHz, the phase angle margin is 85°, the power consumption is 3.6 mW, and the THD is 0.25%. The amplifier is suitable for high output drive.