A 71-dB-dynamic range, 1-dB-step, low-noise programmable gain amplifier based on 018 μm CMOS process was presented. The current model architecture was adopted to achieve R2R common mode input range(CMIR), considering the constrained CMIR of traditional instrument amplifier with three opamps. The internal opamps’ offset voltage and low-frequency 1/f noise were reduced by chopper. The control of gain was achieved by coarse adjustment and fine adjustment, the voltage signal was converted into current signal by coarse adjustment, and the fine adjustment restored the current signal to voltage signal basing on the coarse adjustment, finally wide range and high precision were realized. The simulation results showed that the gain range of -3 dB-68 dB and step of 1 dB were totally obtained; the equivalent input noise from 1 Hz to 100 kHz at 48 dB was 3573 μV, CMRR and PSRR at 1 kHz were 1189 dB and 1206 dB respectively.

A super-regenerative transceiver with low power all-digital frequency locking and sensitivity calibration for the WBAN 402-405 MHz band was designed in a 018 μm CMOS process. A Balun low noise amplifier (Balun-LNA) with the noise-canceling technique was used to reduce the number of passive matching components and adapt to low voltage operation. The frequency tuning of the super-regenerative digital-control oscillator (SR-DCO) was realized by using digitally controlled capacitor arrays, which could eliminate the frequency drift of the oscillator during the quenching operation. The all-digital frequency-locked loop (ADFLL) replaced the frequency synthesizer to reduce the power consumption of the sensor node. The sensitivity calibration loop (SCL) shared components with the automatic amplitude control loop (AACL) to minimize errors, and could dynamically calibrate the receiver sensitivity without interrupting receive conditions. The simulation results show that the receiver sensitivity is -90 dBm, and the power consumption is 189 mW under the 1 V power supply voltage, in which the power consumption of the ADFLL is 78 μW. The power consumption of the transmitter is 196 mW, and the efficiency is 28%.

A digital foreground calibration technique, capacitor recombination technique, is proposed. The convergence speed of LMS algorithm was improved by combining this technique with LMS digital background calibration technique. The proposed algorithm was modeled using a 14-bit SAR ADC with RC hybrid structure. Simulation results show that the convergence speed of LMS algorithm can be improved to within 1 k conversion cycles, and the mean ENOB of the calibrated ADC is increased from 1059 bit to 1379 bit. The mean value of SFDR is increased from 7133 dB to 11293 dB, and the mean value of DNL maximum is increased from 188 LSB to 097 LSB. The mean value of INL maximum is increased from 801 LSB to 088 LSB.

Aiming at the problems of high power consumption and week shaping ability of traditional second-order noise-shaping (NS) successive approximation register analog-to-digital converters (SAR ADC), a third-order NS-SAR ADC with a hybrid error control topology of cascaded integrator feedforward (CIFF) and error feedback (EF) is proposed. A feedback capacitor was added to the system in series with the capacitor digital to analog converter (CDAC). Thus, the filter capacitor was not directly connected to the CDAC. Therefore, the feedback capacitance can be used to adjust the size of the attenuation factor to ensure that the input signal is not attenuated and the feedback signal is attenuated slightly. This EF-CIFF structure provided stronger NS capability and robustness of higher-order NTF. Furthermore, only a small gain and low power dynamic amplifier was needed to realize the residual amplification of EF and CIFF paths. The proposed NS-SAR ADC was designed in a 180 nm CMOS process. When the circuit works at 160 kS/s sampling frequency, its power consumption is only 113 μW at a 18 V supply. When the oversampling rate is 8, the ENOB is 156 bit.

A parameter optimization algorithm for the incremental Σ-Δ modulator is proposed. The coefficient of the integrator in the incremental Σ-Δ modulator was optimized. The two-step search algorithm was proposed to solve and compare the possible optimal coefficient combination for many times. Based on this algorithm, the effective precision and the input sampling rate of the Σ-Δ ADC could be effectively adjusted and optimized. An 16 bit 40 kS/s incremental Σ-Δ ADC was designed. The simulation results show that the proposed optimization design algorithm can increase the ADC input sampling speed from 40 kS/s to 51 kS/s, or increase the ADC ENOB from 1376 bit to 1472 bit without adding additional power consumption.

A 25-28 Gbit/s optical receiver circuit with adaptive equalization and clock data recovery was designed in a 65 nm CMOS technology. The analog front-end adopted a low-bandwidth design to optimize the receiver's sensitivity. A decision feedback equalizer was used to recover the inter-symbol interference (ISI) introduced by the low-bandwidth front-end. In order to adapt to the inter-symbol interference introduced by different rates and process corners, the adaptive equalization of the signal was realized by combining the SS-LMS adaptive algorithm. The reference-less clock data recovery circuit used a frequency discrimination loop to widen the frequency capture range, which embedded a half-rate phase detector (PD) in the equalizer to reduce power consumption and cost. The post-simulation results show that under the parasitic capacitance of the 100 fF photodiode, the maximum gain of the receiving front end reaches 66 dBΩ, the equivalent input noise current at 25% bandwidth is 153 pA·Hz-1/2, and the sensitivity of the optical receiver is -145 dBm. When the supply voltage is 12 V, the overall power consumption of the optical receiver is 1811 mW.

A low-phase-noise cascaded dual phase-locked loop millimeter-wave frequency synthesizer was designed in a 65 nm CMOS technology. A two-stage phase-locked loop cascaded structure was adopted to reduce the influence of bandwidth constraints on the phase noise in band and out of band of the single-stage system in millimeter-wave frequency synthesizer. The vernier structure was adopted in time-to-digital converter to improve the quantization linearity during the time-to-digital convert under PVT changes. The automatic loop gain control technology was used in digital loop filter to adaptively adjust the loop bandwidth to improve the performance of the frequency synthesizer. The noise circulating technology was adopted in oscillator to reduce the injected noise of resonator so as to improve the phase noise of oscillator. The post-simulation results show that the frequency range of the frequency synthesizer is 22-26 GHz under a supply voltage of 12 V. When the output frequency is 24 GHz, the phase noise is -1044 dBc/Hz @1 MHz, and the power consumption is 468 mW.

Folded cascode and Class AB topology (FC-AB) operational amplifiers are widely studied and used. However, it is still difficult for designers to build up a specific operational amplifier quickly and accurately due to various applications. In order to solve this problem, this paper presents a quasi-standard design procedure of operational amplifiers for designers who can complete the circuit design by following this procedure. Current distribution was determined as the starting point and the adjustable point in this design procedure, and the most concerned parameter was set as primary constraint and optimized through multiple iterations. At last, the sizes of devices were obtained by corresponding current and trans-conductance. The design procedures for low noise operational amplifiers have been presented in the form of flow charts. The average error between the theoretical values and the final design values of key device sizes were 1148%. To verify the feasibility of the design procedure, an operational amplifier was designed by using this design procedure and fabricated with a standard 018 μm CMOS process. The concerned electrical characteristics are all met with the design requirements. Its input-referred noise is 108 nV/√Hz, which differs from the target value by only 18%.

A simple, broadband and efficient Class E power amplifier operating in the C-band was designed in a 025 (m GaN HEMT process. To address the problem of large RF choke area in the design of monolithic microwave integrated circuit (MMIC) power amplifier, a finite DC-feed inductance instead of RF choke inductance was used to suppress the effect of the transistor parasitic parameter Cds on the maximum operating frequency. Moreover, a low Q mixed parameter matching network was adopted to match the optimal impedance of the input and output of the power amplifier circuit to the standard impedance of 50 Ω. The post-layout simulation results show that the power-added efficiency is 51309% to 58050% in the 41-49 GHz operating frequency band, with an average gain greater than 11 dB and an output power greater than 41 dBm. The size of layout is 27 mm×14 mm.

A capacitor-less low dropout regulator (LDO) with high stability and good transient characteristic is proposed. The system’s transient response capability was improved by using the push-pull differentiator to detect the changes of output voltage caused by the load’s transient changes, and by increasing the charge and discharge currents of parasitic gate capacitors of the power transistors. After the error amplifier was connected to the buffer stage, the pole at the gate of the power transistor was pushed to the high frequency, and the miller compensation method was adopted to make the system stable within the full load range. The circuit was fabricated in TSMC 65 nm CMOS process, and the core circuit area was 0035 mm2. The tested results show that when the minimum supply voltage is 11 V, the voltage drop is only 100 mV. When the load current changes between 1 mA and 150 mA at 1 μs, the maximum overshot voltage and undershot voltage is 200 mV and 180 mV respectively.

An asymmetric Doherty power amplifier (DPA) with a saturated output power of 44 dBm and an output back-off of 9 dB was designed in a GaN process, with a front driving power amplifier (PA) added for gain increase. Afterwards, by optimizing the impedance matching network of main PA, the λ/4 impedance conversion line could be removed. The output impedance of auxiliary PA was replaced by RC network equivalently, and the phase of output matching was maintained at 0°, thereby ensuring high resistance state during turn-off. Also, the optimal impedance at closing point was directly selected as 50 Ω, thus removing the λ/4 impedance conversion line. The simulation results show that when considering the frequency band of 33-36 GHz, a saturated output power, a power gain, and a power added-efficiency (PAE) of the proposed DPA are higher than 44 dBm, 25 dB, and 50%, respectively. Besides, PAE can be above 347% at the output back-off of 9 dB. In addition, the chip size of DPA is 34 mm*33 mm, and that of driving PA is 15 mm*17 mm.

A clock IP circuit structure suitable for 18/25/33 V wide power supply range is proposed. In order to suppress the influence of the reset pulse signal of the frequency and phase detector (PFD) on the performance of the charge pump (CP) when the power supply changes, a constant reset pulse width generation circuit is proposed. An ultra-low mismatch CP was used to increase the output current matching. The IUP/IDN current mismatch was less than 009% when the control voltage varied within a range of 02-(VDD-02) V. At the same time, a ring oscillator (RO) with symmetrical load structure was introduced to suppress the impact of power supply change on the loop performance. The whole circuit was designed and simulated in SMIC 180 nm CMOS process, and the output frequency was 100-500 MHz. The simulation results show that when the input reference frequency is 50 MHz and the output frequency is 250 MHz, the power consumption is 82/125/184 mW at 18/25/33 V supply voltage, respectively, the reference spurious is lower than -74 dBc, and the output rms jitter is 18 ps.

Aiming at the problems of the traditional four-phase clock generator circuit, such as the overlapping of clock waveform signals and the leakage of charge pump, a new four-phase clock generator circuit with adjustable duty cycle is proposed. The circuit added a delay unit module between the clock signals that may overlap in each two phases, and adjusted the duty cycle of the output clock signal by controlling the delay time to avoid the overlap of the clock. Additionally, the delay unit was adapted to realize the controllable delay under the condition of external bias voltage. The simulation results based on a 55 nm CMOS process show that the four-phase clock generator circuit can output four-phase non-overlap clock signal stably in the clock input frequency range of 10-50 MHz, and can drive the 10-stage charge pump to pump 112 V efficiently at a supply voltage of 12 V. The tested results obtained from fabricated circuits show that the four-phase clock generator circuit can produce non-overlapping four-phase clock waveforms, and the clock output phase can meet the driving requirements of the charge pump.

A fully integrated flipped voltage follower (FVF) based capacitor-less low-dropout regulator (LDO) with fast transient response and wide input voltage range is presented. Only two capacitors were used as the detection module to dynamically adjust the transient response without additional auxiliary circuit. The method could make up for deficiencies of the traditional LDO, such as low integration, large area, high power consumption and poor transient response. The proposed circuit was fabricated in TSMC 180 nm process. The simulation results show that the circuit’s dropout voltage is 200 mV, the quiescent current is 36 μA, the input voltage range is 2-4 V, the low frequency PSRR is -59 dB. The generated maximum overshoot is 50 mV, the undershoot is 66 mV, and the transient voltage recovery time is 300 ns when ILOAD changes between 0 mA and 10 mA with an edge time of 150 ns and a load capacitance 30 pF.

An improved level shift circuit was designed, which used a cross-coupling structure to significantly improve the noise immunity of high voltage gate drive integrated circuits (HVIC) without significantly increasing the circuit complexity. The entire driver was designed in a 035 μm 600 V BCD process. The simulation results show that the driver can achieve up to 125 V/ns of dV/dt noise immunity and allow negative VS voltage overshoot up to -96 V at 15 V supply voltage. In addition, this paper theoretically analyzes the propagation delay of the improved level shift circuit. Compared with the traditional HVIC, the overall propagation delay of the HVIC has been optimized and reduced to about 54 ns.

In buck converter, in order to obtain high efficiency under different load conditions, pulse width modulation (PWM) is often used under heavy load, and pulse frequency modulation (PFM) is used under light load, so the mode switching signal is needed to control the working state of the whole buck converter. At the same time, the mode switching signal can also be used to adaptively change the grid width of the power stage circuit, which reducing the grid capacitance of the power tube and improving the efficiency of the whole circuit. An adaptive peak current mode switching circuit was designed to generate a mode switching signal. Its principle is to monitor the change of peak current and generate a peak voltage. After comparing the peak voltage with a reference voltage, the mode switching signal is obtained to decide whether the buck converter adopts PFM mode or PWM mode. The simulation results show that the circuit can switch smoothly between the two modulation modes in the range of load current from 05 mA to 500 mA, and its peak efficiency can be improved to over 94%.

In order to achieve higher conversion efficiency for buck DC-DC converter under light and heavy load conditions, a segmented structure and an NMOS transistor with smaller conduction resistance were used as input stage, and a PWM/PFM dual modulation mode was used. To solve the switching problem of PWM/PFM modulation signals, the zero current detection method was adopted for switching. By using the difference between (DCM) and (CCM) inductance voltages when the low-side NMOS was turned on to detect the period when the inductance voltage of the low-side NMOS was greater than zero when it was turned on. When the period of inductance voltage greater than zero was greater than 2, it was in DCM mode, and the circuit automatically used PFM modulation and turned off a part of the power MOSFET to reduce the switching frequency and parasitic capacitance of the power MOSFET to optimize the light-load efficiency. Otherwise, it was in CCM mode, and the circuit used PWM modulation. The simulation results show that the DC-DC converter can switch smoothly between the two modulation modes in the range of 10-1 000 mA of load current, and the peak efficiency can be increased to more than 96% at 800 mA.

A dual-phase peak current-mode control buck converter chip with large load capability was designed. By operating in dual-phase, the chip was guaranteed to hold high efficiency under heavy load. Considering the extra switching loss from two phases during light load, an optimized light load mode was proposed. It used the control voltage generated by the error amplifier in the voltage loop of the current-mode control loop as the load position detector. When the load was stepped down, the active phase could be changed from two to one. As the load turned into ultra-light, the system could also work in discontinuous conducting mode to further improve the efficiency. It was designed in a 035 μm BCD process. Simulation results show that under the conditions of 12 V input voltage, 1 V output voltage, 500 kHz switching frequency and 20 A maximum load, compared with the traditional single-phase peak current-mode, the maximum efficiency can be improved by about 3 percentage point under a heavy load of 20 A and can be improved by about 10 percentage point under a light load of 05 A.

Aiming at the shortcomings of environmental energy harvesting systems such as high output voltage ripple and efficiency changing with load, an energy harvesting system with high conversion efficiency and low output voltage ripple in a wide load range is proposed. The system was based on the optimized conduction time (OOT) control method to regulate the output ripple, which solved the problem of a large ripple in the case of small load capacitance and light load in the traditional control method. In addition, the adaptive system clock frequency (ACF) control method could improve the efficiency of traditional methods in light loads, and maintain high efficiency in a wide range of loads. A 180 nm CMOS technology was used to verify the design of the energy harvesting system. The simulation results show that the peak efficiency of the designed energy harvesting system is 8975%, and the lowest efficiency is 8375% in the range of 1 mA load current, which is more than 7 percentage points higher than that of similar systems. The ripple value decreases from 17796 mV to 2356 mV at 02 μF load capacitance.

Electromagnetic shielding materials can limit the transmission of electromagnetic energy, avoid the electromagnetic interference and reduce the risk of leakage. Therefore, they are increasingly used in the military and civil fields. With unique two-dimensional structure and excellent physical and chemical properties, graphene fits the rapid development of flexible electronic devices well. Based on the theory of electromagnetic shielding, this paper involves the design ideas and preparation methods according to the classification of pure and composite graphene films, reviews the research progress of graphene-based electromagnetic shielding film materials in recent years, and prospects its development in view of the application needs.

The shoe energy harvester used to collect all kinds of mechanical energy generated by foot movement and convert it into electric energy has great application prospects in wearable micro sensors, and has attracted extensive attention from domestic and foreign researchers. This paper systematically investigates the research progress of shoe energy harvesters at home and abroad. According to the different excitation generated by foot movement, shoe energy harvesters are divided into two types: direct loading type and inertia excitation type. The structure, working principle and advantages and disadvantages of these two types of energy harvesters are emphatically analyzed, and the development trends of shoe energy harvesters are summarized.

Flexible electronic technology has developed rapidly in recent years, and more and more flexible electronic systems require flexible, high-performance integrated circuits to achieve data processing and communication. High performance flexible integrated circuits can be obtained by thinning silicon chips, but the performance of silicon chips may change after thinning, and defects or breakage are easy to occur in the process of preparation, transfer and packaging, resulting in chip performance degradation or even failure. Therefore, the preparation process and flexible packaging technology of ultra-thin chips are very critical to the preparation of high reliability flexible chips. In this context, this paper reviews the research progress of mechanical and electrical properties of flexible silicon chips, introduces the thinning process and flexible packaging frontier technology of several ultra-thin silicon chips, and summarizes and prospects the application and development of ultra-thin silicon chips in the field of flexible electronics, so as to provide reference for further research on flexible silicon-based chip technology.

With the progress of infrared technology and detector performance, medium-wave and short-wave infrared technology has been increasingly used in civil, military and aerospace fields because of its better imaging performance in bad weather. As the key module connecting detector array and backward image processing circuit, the readout circuit has important influence on the performance of medium wave and short wave infrared camera system and determines the final image quality. The development status of medium wave and short wave infrared image sensor’s readout circuit is summarized in this paper. The noise, dynamic range, frame rate and other problems are analyzed. And the solutions to the above problems are presented. Finally the future design prospect of readout circuit is also discussed.

Resistive MEMS semiconductor gas sensors have been widely used in the fields of ambient air quality monitoring and toxic and harmful gas detection. However, due to the high power consumption, this kind of sensor is difficult to be applied to portable gas detection system. The research progress of resistive MEMS semiconductor gas sensor with low power consumption in recent years is reviewed in this paper. How to realize resistive MEMS semiconductor gas sensor with low power consumption from the aspects of gas sensing materials, sensor structure and sensor module integrated circuit are discussed. And the future development direction of resistive MEMS semiconductor gas sensor with low power consumption is prospected.

A GaN high electron mobility transistor (HEMT) with a P-GaN gate coupled with a hybrid doped cap layer structure is presented to further improve the threshold voltage and breakdown voltage of P-GaN gate HEMT devices. The new device controlled the overall polarization effect by using a hybrid doped cap layer structure, which further depleted the two-dimensional electron gas in the channel region below the hybrid cap layer and raised the threshold voltage. The device also controlled the electric field distribution on the right side of the gate in the reverse blocking state, which enhanced the electric field concentration phenomenon at the gate edge, and raised the breakdown voltage of the device. Sentaurus TCAD simulation results reveal that the novel structure device's breakdown voltage is boosted from 593 V to 733 V, a 24% increment, and the threshold voltage is boosted from 0509 V to 1323V, a 33% increment when compared with that of the common P-GaN gate enhanced device.

In order to reduce the on-resistance of the trench MOS devices, a scheme of injecting N-type impurity into the body region of the conventional trench MOS devices was proposed, and the concentration distribution of impurity in the body region was optimized to reduce the on-resistance. The simulation results show that the specific on-resistance and threshold voltage can be reduced by 13% and 218% respectively when arsenic is injected into the N+ source area at an energy of 300 keV and a dose of 7×1012 cm-2. After the contact hole is etched, phosphorus is injected. Under the condition of energy of 100 keV and dose of 4×1012 cm-2, the specific on-resistance is reduced by 43% and the threshold voltage is almost unchanged.

In order to improve the sensitivity of weak pressure sensors, a pressure sensor with excellent performance was fabricated by using microstructure to produce piezo resistive effect. Three kinds of graphene pressure sensors with different structures were studied. The layout structure, process preparation and material characterization of graphene pressure sensors were designed and studied. Finally, the sensitivity of the three graphene pressure sensors with different structures was tested. The experimental results show that the graphene pressure sensor with network structure has high sensitivity, the sensitivity can reach 0303 kPa-1 at low pressure (0-200 Pa), and the lowest pressure can be detected at 245 Pa. The graphene pressure sensor with network structure is a high performance pressure sensor that can sense weak pressure changes.

The 4H-SiC MOSFET with a shallow trench is designed and studied to reduce the specific on-resistance and turn-on loss. The proposed structure shows a lower CGS and CGD/CGS because of the shallow trench in the JFET region. By introducing the highly doped N+ region under the trench, the electron quasi-fermi potential across the inversion layer along the interface of SiC/SiO2 is increase, which improves the current capability of the MOSFET and reduce the specific on-resistance Ron. And the simulation results demonstrate that the specific on-resistance of the proposed structure is reduced by 14% and 178% compared with that of the planar MOSFET and split gate MOSFET, respectively. Besides, the turn-on loss is also reduced by 20% compared with that of the planar MOSFET.