Microelectronics, Volume. 53, Issue 4, 741(2023)

Design and Optimization of 12-kV SiC Planar Inversion MOSFET Using Shallow Trench N+ Injection in the JFET Region

ZHANG Bingke, LI Xuhan, WANG Rui, DONG Jiajun, CHANG Shucheng, SUN Junmin, BAI Xue, LI Zheyang, and JIN Rui
Author Affiliations
  • [in Chinese]
  • show less

    The 4H-SiC MOSFET with a shallow trench is designed and studied to reduce the specific on-resistance and turn-on loss. The proposed structure shows a lower CGS and CGD/CGS because of the shallow trench in the JFET region. By introducing the highly doped N+ region under the trench, the electron quasi-fermi potential across the inversion layer along the interface of SiC/SiO2 is increase, which improves the current capability of the MOSFET and reduce the specific on-resistance Ron. And the simulation results demonstrate that the specific on-resistance of the proposed structure is reduced by 14% and 178% compared with that of the planar MOSFET and split gate MOSFET, respectively. Besides, the turn-on loss is also reduced by 20% compared with that of the planar MOSFET.

    Tools

    Get Citation

    Copy Citation Text

    ZHANG Bingke, LI Xuhan, WANG Rui, DONG Jiajun, CHANG Shucheng, SUN Junmin, BAI Xue, LI Zheyang, JIN Rui. Design and Optimization of 12-kV SiC Planar Inversion MOSFET Using Shallow Trench N+ Injection in the JFET Region[J]. Microelectronics, 2023, 53(4): 741

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category:

    Received: May. 1, 2023

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230216

    Topics