A low cost 2 kbit EEPROM memory was designed in a 350 nm 2-poly 3-metal EEPROM process for low frequency passive RFID applications. The design minimized the layout area by optimizing the Dickson charge pump and the readout circuit, while ensuring that the memory capacity could meet most usage scenarios. The optimized Dickson charge pump provided a stable voltage boost from 3.3 V to 16 V in 10 μs with the power consumption of 334 μW. The readout circuit was based on detecting the threshold voltage of the NCG device to discriminate the stored logic value, which eliminated the need for a high precision current reference circuit and a sensitive amplifier with high gain, effectively reducing the overall circuit area. The low cost 2 kbit EEPROM operated at 3.3 V and was capable of 32 bit parallel input and one-bit serial output, with a total chip area of 0.14 mm2, effectively reducing the complexity and manufacturing cost of low frequency passive RFID designs.