A low power and low reference spur charge pump PLL with high matching charge pump and precision automatic frequency calibration circuit was designed. It consisted of D-trigger PFD, 5 bit digital programmable frequency modulation LC VCO, 16-400 programmable frequency divider and automatic frequency calibration (AFC) circuit. An improved charge pump circuit was designed to reduce the current mismatch of the high matching charge pump by increasing the output impedance of the current mirror. By adopting the frequency band preselection fast search method, the AFC circuit locked the frequency accurately with lower voltage gain of LC VCO, extended the range of locked frequency, and kept the output reference spurs lower enough. The PLL was designed in a 40 nm CMOS process with 1.1 V power supply. The simulation results show that the charge pump matched voltage range is 0.19-0.88 V, the oscillation frequency range is 5.9-6.4 GHz, the power is less than 6.5 mW@6 GHz, and the maximum current mismatch is less than 0.2%@75 μA. When the signal frequency is 6 GHz, the output phase noise is -113.3 dBc/Hz@1 MHz, and the reference spur is -62.3 dBc.