Fig. 1. Schematic of OPE^[1]. (a) Optical proximity effect; (b)(c) optical proximity correction and wafer pattern effect diagram

Fig. 2. Development of optical proximity effect technology

Fig. 3. Schematic of OPC based on edge movement and ILT based on pixel value adjustment^[7]. (a) Schematic of EPE between the target layer and simulated contours on the wafer; (b) schematic of traditional OPC based on edge fragment movement; (c) schematic of ILT based on pixel value adjustment

Fig. 4. Schematic of ILT optimization iteration. (a) Optical imaging simulation process and ILT iterative optimization illustration; (b) mask shape and wafer imaging contour obtained after the M and M+1 optimization iterations, after M+1 iterations, the EPE requirement is met

Fig. 5. Applications of ILT in lithography performance improvement. (a) SEM images obtained by ILT and traditional OPC, respectively, ILT significantly improves the shortening and rounding of wire ends^[46]; (b) relationship between SRAF complexity and five different logical pattern process windows^[47]; (c) enhancing process window by increasing EPE on ILT^[20]; (d) (e) reduction of EPE in patterns by ILT^[20]

Fig. 6. Validation example of full-chip ILT in DRAM^[31]

Fig. 7. ILT calculation strategy involving full-chip layout splitting, Manhattanizing, and merging^[31]. (a) Process of full-chip ILT calculation; (b) comparison of curvilinear and Manhattanized layouts

Fig. 8. Stitching in full-chip ILT calculation^[31]. (a) Edge stitching errors caused by traditional layout splitting, ILT calculation, and stitching method; (b) full-chip ILT calculation resolves edge stitching issues

Fig. 9. ILT MRC strategy. (a) MRC inspection rules for curvilinear layouts proposed by Mentor, including curvature, minimum area, and minimum spacing^[56]; (b) local areas with significant curvature in curvilinear layouts^[56]; (c) curvature inspection of layouts based on circular rolling^[57]; (d) example of MRC inspection in D2S ILT products^[31]

Fig. 10. Data flow diagram from layout OPC, MPC, and MDP to wafer exposure. (a) Mask data processing flow; (b) results of mask data processing at different steps

Fig. 11. Mask manufacturing process and imaging principle. (a)‒(d) Manufacturing process of chrome-glass binary masks; (e) schematic diagram of imaging principle

Fig. 12. Electron scattering process and electron energy deposition distribution in the electron beam exposure process. (a) Schematic diagram illustrating the electron scattering process during electron beam exposure^[60]; (b) distribution of electron energy deposition^[61]; (c) mathematical model of the electron proximity effect^[62]

Fig. 13. CD deviation in mask manufacturing above and below the 14 nm technology node^[63]

Fig. 14. Two strategic flows for establishing mask manufacturing process models^[60]. (a) Process of establishing mask manufacturing process models based on first-principles calculations; (b) process of establishing a compact model based on experimental test data

Fig. 15. MPC flow and schematic diagrams for shape and dose corrections. (a) Mask MPC flow; (b) schematic diagram of uncorrected pattern (top) and mask exposure profile after exposure (bottom); (c) geometric correction based on edge fragment and edge movement (top) and exposure profile of corrected pattern after exposure (bottom); (d) dose correction based on mask area segmentation (top) and exposure profile of corrected pattern after exposure (bottom)

Fig. 16. Mask data preparation. (a) Schematic of VSB machine achieving specific shapes of electron beams through two electromagnetic coils; (b) rule-based MDP

Fig. 17. MB-MDP^[73]. (a)(b) Overlapping electron beam MDP; (c) ideal pattern (top), patterns generated by MB-MDP (middle), and simulated patterns (bottom) at three different shot counts

Fig. 18. Schematic of fitting curvilinear patterns using VSB shots^[35]

Fig. 19. Mask pattern processing flow based on MWCO and MWCO method^[35]. (a) Mask pattern processing flow based on MWCO; (b) schematic of MWCO method; (c) (d) traditional and based-MWCO method of processing mask graphics by OPC team and mask shop

Fig. 20. Mask pattern processing flow and MPC process for curvilinear patterns. (a) Mask pattern processing flow^[76]; (b) mask rule check and MPC process for a curvilinear pattern^[76]; (c) equidistant SRAF mask pattern scheme^[77]

Fig. 21. Principle of multi-electron beam machine^[78]. (a) Principle of multi-electron beam machine by IMS company; (b)(c) APS system based on MEMS construction; (d) schematic diagram of pixel array exposure achieved by one exposure field with one exposure pulse; (e) pixel addressing for multi-dose exposure

Fig. 22. VSB and MBMW writing versions^[79]. (a) Comparison of multi-electron beam and VSB lithography machine lithography; (b) EUV layout modified using ILT; (c) SEM image of the mask pattern produced using a multi-electron beam machine to write the layout

Fig. 23. Quantification of ILT mask based on SEM contour extraction^[85]. (a) Red line represents the contour extracted from the SEM image; (b) statistical results of EPE obtained based on contour analysis; (c) flowchart of Synopsys analysis based on image contour extraction

Fig. 24. Machine learning generates full-chip SRAF^[29]. (a) Machine learning training to generate SRAF and DCNN; (b) DCNN generated based on Fig. (a) generating SRAF and embedding it into the ILT process; (c) machine learning SRAF generation method reduces the computation time for SRAF generation