Laser & Optoelectronics Progress, Volume. 60, Issue 19, 1926001(2023)

Modeling and Analysis of Parasitic Capacitance in 4-Transistor Pixels Based on Self-Alignment Technique

Yajuan Du1,2, Jing Gao1,2、*, Zhiyuan Gao1,2, and Kaiming Nie1,2
Author Affiliations
  • 1School of Microelectronics, Tianjin University, Tianjin 300072, China
  • 2Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin 300072, China
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    Figures & Tables(10)
    Schematic of the parasitic capacitance of the FD node
    Schematic diagram of the potential distribution of transfer gate and FD
    Schematic representations of the change in FD node with increasing injection dose. (a) Low injection dose; (b) increased injection dose; (c) large injection dose
    Structure of FD node simulated by TCAD
    Trends of the FD parasitic capacitance with the injection dose
    Variation of the electrostatic potential at the boundary of transfer gate with the injection dose
    Optimization of the potential under the sidewall by the tilt injection. (a) Only one vertical injection performed at the FD node; (b) "vertical + tilt" injection performed at the FD node
    Dependence between FD parasitic capacitance and injected energy
    Dependence between FD parasitic capacitance and VFD
    Dependence between FD parasitic capacitance and LFD
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    Yajuan Du, Jing Gao, Zhiyuan Gao, Kaiming Nie. Modeling and Analysis of Parasitic Capacitance in 4-Transistor Pixels Based on Self-Alignment Technique[J]. Laser & Optoelectronics Progress, 2023, 60(19): 1926001

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    Paper Information

    Category: Physical Optics

    Received: Apr. 11, 2022

    Accepted: Jun. 13, 2022

    Published Online: Sep. 28, 2023

    The Author Email: Jing Gao (gaojing@tju.edu.cn)

    DOI:10.3788/LOP221253

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