Microelectronics
Co-Editors-in-Chief
Xiaojun Fu

Jan. 01, 1900
  • Vol. 53 Issue 3 1 (2023)
  • HAN Wentao, MING Pingwen, XIAO Hang, ZHANG Zhong, LI Jing, and YU Qi

    A correctable 12-bit C2C capacitor array hybrid structure successive approximation analog-to-digital converter (SAR ADC) is proposed, whose digital-to-analog converter (DAC) consists of a low 6-bit split C2C DAC array and a high 6-bit binary DAC array. The problem that the total capacitance is too large in the medium and high-precision binary SAR ADC and the problem that the fractional bridge capacitance of the segmented binary DAC cannot be matched with the unit capacitance can be solved by the proposed hybrid structure DAC. This structure can significantly reduce the dynamic power consumption of the entire ADC. In addition, the high terminal capacitance and the low 2-6 bit quantization capacitance are split into two equal capacitances to introduce redundancy, so that the capacitance weight of the ADC can be calibrated, which reduces the influence of capacitance mismatch and parasitic capacitance. Finally, to avoid the problem of the reset delay of the upper-level board, the method of high 6-bit DAC sampling is adopted, and a terminal capacitor of unit capacitance is introduced into the high-6-bit DAC to make up for the incompleteness of reference voltage range. The simulation results show that at 15 V supply voltage, the ADC's overall power consumption is only 11184 μW, the ENOB is 1249 bit, the SFDR is 9146 dB, and the SNDR is 7697 dB.

    Jan. 01, 1900
  • Vol. 53 Issue 3 359 (2023)
  • GE Binjie, LI Yan, YU Hang, MA Siguang, and XIE Qingguo

    In conventional SAR ADC, most time of every conversion cycle is used for quantization, and only a little time is left for sampling, thus high driving capability buffer and low Ron sampling switch are indispensable. Otherwise, serious nonlinearity will generate. The proposed time-interleaved sampling architecture could extend the sampling time of SAR ADC to equal to quantization time without reducing the quantization time and conversion rate, thus greatly reducing the power consumption of ADC driver. This paper designed and implemented a 40 Msps 10 bit asynchronous SAR ADC based on Fujitsu 55 nm CMOS technology. The measurement results show the ENOB of the converter is 97 bit.

    Jan. 01, 1900
  • Vol. 53 Issue 3 366 (2023)
  • ZANG Jiandong, YANG Weidong, LI Jing, ZHANG Shili, and LIU Jun

    A 12-bit 45 GSPS digital-to-analog converter (DAC) in 013 μm SiGe BiCMOS technology is described Firstly this paper presents an evaluation of the technology constraints on the design of low latency time and high conversion rate for DAC. In order to achieve low latency and high speed, a special low latency architecture and current-mode logic (CML) have been used. And the introduction of innovative output modes bypassing the limits of sin(x)/x found in most DACs, and extending significantly DAC linearity. And architectural breakthrough, minimizing capacitive and inductive parasitics on critical nodes, allowed an extension of DAC usable output bandwidth up to 59 GHz. The converter has been fabricated, and test results showed that, at 45 GHz guaranteed conversion rate, the latency time is less than 35 clock cycles. Spurious free dynamic range (SFDR) for the described converter is 57 dBc at a clock rate of 45 GHz and an output frequency of 4455 GHz.

    Jan. 01, 1900
  • Vol. 53 Issue 3 372 (2023)
  • LIU Qingyuan, WANG Zongmin, ZHANG Tieliang, LIU Bo, and HUO Miao

    Based on the pre-amplifier array, an average resistor network was designed to reduce voltage offset. The causes of boundary effect of resistance network were analyzed. Redundant pre-amplifier design and ring average network design are adopted, and unequal termination resistance design is proposed to alleviate the boundary effect. The node matrix current equation was proposed. It could provide the optimization direction for the design of average resistance network. After the boundary effect improved by using the node matrix current equation design, using the pre-amplifier array in a 12-bit folding-interpolation ADC, the ENOB is 1032 bits and the SFDR is 743 dB at a sampling frequency of 25 GSPS and a 08 V sinusoidal input of 1242 GHz.

    Jan. 01, 1900
  • Vol. 53 Issue 3 379 (2023)
  • YUAN Bo, WU Xiulong, XIE Zhuoheng, ZHAO Qiang, and QIN Mou

    A high power wideband SPDT RF switch was designed and implemented in a 013 μm CMOS SOI process. The RF switch was an absorption RF switch with a series and parallel topology. The negative voltage bias design was applied to reduce the insertion loss and improve isolation. The stacked-MOSFET structure was applied to improve the input 1 dB compression point of the switch. The test results show that in the frequency range from 100 MHz to 12 GHz, the insertion loss is less than 15 dB, the minimum isolation is 31 dB, and the minimum input 1 dB compression point is 40 dBm. The chip size is 11 mm × 11 mm.

    Jan. 01, 1900
  • Vol. 53 Issue 3 385 (2023)
  • WAN Jialong, and HE Jin

    A millimeter-wave dual-wideband low noise amplifier (LNA) was designed. It could reconfigure the passive inductors through RF switches, so that it could operate at the center frequencies of 28 GHz and 32 GHz, respectively, and is suitable for millimeter-wave 5G communications. The reconfigurable low noise amplifier (RLNA) has been designed in a 55-nm CMOS process. The post-simulation results show that, with a switch voltage (Vs) of 0 V, the RLNA has a gain of 23 dB, an input 1 dB compression point (IP1dB) of -54 dBm at the center frequency of 28 GHz, and a noise figure of 41-44 dB over -3-dB bandwidth from 261-322 GHz (61 GHz). While with a Vs of 12 V, the RLNA achieves a gain of 20 dB, an IP1dB of -75 dBm at the center frequency of 32 GHz, and a noise figure of 44-47 dB over -3-dB bandwidth from 28-34 GHz (6 GHz). The chip has an area of 070×055 mm2 and consumes 252 mW at a supply voltage of 12 V.

    Jan. 01, 1900
  • Vol. 53 Issue 3 390 (2023)
  • YANG Yonghui, ZHANG Jinlong, ZHANG Guangsheng, HUANG Dong, and ZHU Kunfeng

    A rail to rail operational amplifier was designed based on CMOS technology. The whole circuit includes bias circuit, input stage, output stage and ESD protection circuit. A new architecture was used in the input stage of the circuit. Rail to rail input could be realized through a pair of depletion NMOS tubes as input tubes. At the same time, the common source common grid structure was adopted in the input stage, which could provide high common mode input range and gain. In the output stage, class AB output stage is used to obtain full swing output. At the same time, the ESD protection circuit adopts the traditional ggmos circuit, and the withstand voltage is greater than 2 kV. After simulation, it can be seen that the input bias current of the circuit is 150 fA. When the load is 100 kΩ, the maximum and minimum output voltage can reach the range of 20 mV from the power rail and ground rail. When the power voltage is 5 V, 80 dB CMRR and 120 dB gain can be obtained, the phase margin is about 50 °, and the unit gain bandwidth is about 15 MHz.

    Jan. 01, 1900
  • Vol. 53 Issue 3 396 (2023)
  • OU Hongqi, LIU Yukui, FU Xiaowei, HAUNG Lei, ZHU Yukai, YIN Wanjun, and WANG Lu

    A high voltage and low power comparator circuit was presented. The circuit based on 05 μm CMOS IC process was designed with differential pair single ended output structure, and high voltage PMOS tail current was used to realize the purpose of reducing power consumption. The results show that the static current of the circuit is about 825 μA, the operating voltage range is 3-18 V, the input offset voltage is 5 mV, the input offset current is about 6 fA, and the input bias current is about 25 pA. The circuit is suitable for analog circuits with low power and high voltage.

    Jan. 01, 1900
  • Vol. 53 Issue 3 402 (2023)
  • CUI Huarui, PU Lin, TANG Guangqing, LI Tao, CHEN Hao, and LIAO Pengfei

    Based on the analysis of traditional ring oscillators, and a high precision and low temperature coefficient oscillator with switched-capacitor is proposed. A frequency based negative feedback circuit with switched capacitor circuit was designed for the oscillator, in which the precision and the temperature coefficient of output frequency was only dependent on external resistor and integrated capacitor. With an appropriate chosen external resistor, a high precision clock with low temperature coefficient could be achieved. The circuit was designed and implemented in a 06 μm standard CMOS process. The simulation results show that the frequency error is less than 174% and the frequency drift over temperature is less than 811×10-5/℃ when the output frequency is 5 MHz.

    Jan. 01, 1900
  • Vol. 53 Issue 3 408 (2023)
  • ZHANG Jun’an, XIAO Yi, XU Jingui, LI Xinxing, and LI Tiehu

    A 16-bit voltage output type digital-to-analog converter (DAC) with 10-bit resistor string divider and 6-bit interpolation structure was designed. The high 10-bit element consisted of a 1 024 resistors string voltage divider network. The lower 6-bit element was made of 64 op-amp input stage interpolation structure. Both of them were linearly superimposed by thermometer, which structurally ensured the monotonicity of the 16-bit D/A converter. The output amplifier of the D/A converter adopted PMOS input folded cascode, Class AB output buffer structure and multi-stage nested Miller compensation (NMCNR). The stability under high DC gain and large capacitance load was realized. The 16-bit D/A converter was designed in a 06 μm CMOS process. The supply voltage was set at 5 V. The simulation results show that the differential nonlinear error (DNL) is 035 LSB, the integral nonlinear error (INL) is 305 LSB, the set-up time is 612 μs, the spurious-free dynamic range (SFDR) is 9341 dB, and the power consumption is 1842 mW. With a 470 pF capacitor load, the output op-amp DC gain is 15063 dB, the unit gain bandwidth is 159 MHz, and the phase margin is 6584°.

    Jan. 01, 1900
  • Vol. 53 Issue 3 413 (2023)
  • XU Yamei, ZHANG Wanrong, NA Weicong, JIN Dongyue, XIE Hongyun, LIANG Yan, and CAI Ziteng

    A low voltage low power active inductor (LVLPAI) is proposed. It consisted of a novel positive transconductor, a negative transconductor and a voltage conversion module. Among them, the voltage conversion module was connected to the output terminal of the negative transconductor and the input terminal of the positive transconductor. Furthermore, the PMOS transistor in the novel positive transconductor was adopted, and its gate and the substrate were tied together. In this way, the active inductor not only could operate under low voltage and but also had low power dissipation at different frequencies. Based on the 018 μm RF CMOS process, the LVLPAI was verified and compared with the conventional AI. The results indicate that for the LVLPAI and the conventional AI under three inductance values of 3 326 nH at 15 GHz, 1 403 nH at 27 GHz, and 782 nH at 44 GHz respectively, the operation voltages of the former and the latter are 08 V, 1 V 12 V and 15 V, 16 V, 17 V, so the corresponding decreases in voltage are 467%, 375%, 294% respectively. The power consumptions are 008 mW, 025 mW, 053 mW and 014 mW, 031 mW, 062 mW, so the corresponding decreases in power are 429%, 194%, 145% respectively.

    Jan. 01, 1900
  • Vol. 53 Issue 3 419 (2023)
  • GAO Wenjing, ZHANG Wanrong, WANG Xiaoxue, LI Nanxing, REN Yangui, and WU Yinfeng

    A novel high linearity active inductor with enhanced characteristics of quality factor (Q)-frequency (f) and inductance value (L)-frequency (f) was proposed, which is mainly composed of a negative transconductor, a novel positive transconductor, a Q-enhanced modulation module, a feedback resistance, a two-stage level shift circuits and a negative transconductor shunt branch. By the cooperation among the above multiple circuit units and the joint tuning of the constructed three external bias terminal voltages, the active inductor not only had a high Q values and had ability to make the Q values be able to be ajusted independently relative to the inductance values, but also the high Q peaks and inductance values could remain almost unchanged at different frequencies, and at the same time had high linearity. The verification results show that at 6 GHz, the Q value can vary from 275 to 4 471 with the tuning percentage of 1768%, while the inductance value variation is only 15%; at the operating frequencies of 48 GHz, 52 GHz, 56 GHz and 6 GHz, the Q peak values of 4 480, 4 469, 4 473 and 4 471 with a variation of only 024% are obtained, respectively, while the inductance values are 7532 nH, 7467 nH, 7909 nH and 7977 nH with a change of only 63% respectively; the -1 dB compression point of the inductance value is -13 dBV.

    Jan. 01, 1900
  • Vol. 53 Issue 3 425 (2023)
  • KANG Yanxin, XU Weilin, and LI Haiou

    Aiming at the problem of single input voltage and narrow available power range in traditional TEG energy harvesting system, a DC-DC converter suitable for polarity reversal thermoelectric energy harvesting is proposed. The bipolar input buck-boost topology can adaptively collect bipolar input thermoelectric energy, and increase the energy storage buck-boost circuit, which effectively broadens the available power range under heavy load, ensures the stability of output voltage, and collects multiple buck-boost energy under light load, significantly improves the conversion efficiency of light load and ensures the endurance of the system. The maximum power tracking method adopts the open circuit voltage method with simple structure and high tracking efficiency. The 180 nm CMOS process simulation results show that the conversion efficiency of the proposed energy harvesting system under light and heavy load conditions is higher than 85 %, the maximum conversion efficiency is 9326% ( VTEG=500 mV, RS=210 Ω ), the maximum power tracking efficiency is 9952% ( VTEG =-600 mV ), the minimum operating input voltage of the circuit is ±25 mV, and the 18 V output voltage ripple under heavy load is less than 30 mV.

    Jan. 01, 1900
  • Vol. 53 Issue 3 431 (2023)
  • LI Weiye, LI Wenchang, JIAN Haifang, RUAN Wei, WU Honghao, LIU Jian, and YIN Tao

    A current-based temperature sensor chip was designed and implemented. The influence of temperature measurement principle and Early effect on temperature measurement accuracy was analyzed, and a collector-emitter voltage compensation circuit was proposed. The transfer function between the output current and the temperature was linearized by using a set of current mirrors and matched resistors. By this way, the chip’s measurement linearity and accuracy were improved. A reverse bias protection circuit was designed to increase the reverse voltage that the chip can withstand. The chip was designed and fabricated in a 40 V complementary bipolar process. The measurement results show that the nonlinear error of the chip is ±02 ℃, and the temperature measurement accuracy is less than ±03 ℃in the temperature range of -55~150 ℃.

    Jan. 01, 1900
  • Vol. 53 Issue 3 438 (2023)
  • CHEN Kairang, WANG Bing, WANG Youhua, and YANG Yujun

    A detailed design progress of an asynchronous two-stage pipelined SAR-ADC was introduced. In order to achieve a flexible clocking scheme, a self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the sub-ADCs and the gain-stage to reduce the static power consumption of the ADC. A 3-stage capacitive charge pump works as the gain-stage to alleviate the design difficulty and further reduce the power consumption. Finally, a 14 bit asynchronous ADC was designed and simulated in 018-μm CMOS process. Post-layout circuit simulations show that the ADC achieves a SNDR of 835 dB while consuming 239 μW with a sampling rate of 10 kS/s. The corresponding FoMs is 1767 dB.

    Jan. 01, 1900
  • Vol. 53 Issue 3 444 (2023)
  • GUO Zhongjie, GUO Youmei, LI Chen, SU Changxu, WANG Yangle, WANG Bin, and WU Longsheng

    In order to suppress the influence of dark current of pixel array in the exposure stage on the dynamic range and output image quality of image sensor, based on the synchronous adaptive dark current tracking mechanism, an integrated compensation method for dark current at the front of the readout circuit is proposed. While sampling and outputting the effective photoelectric signal, the influence of dark current was eliminated synchronously in the passive processing stage. This method not only compensated for the influence of dark current in different areas on the effective photoelectric signal, but also solved the attenuation problem of the dynamic range of the readout circuit by the traditional dark current elimination method. Based on this scheme, a 752×512 array scale CMOS image sensor was designed in a 55 nm CMOS process, including detailed circuit design, layout design and back-end physical verification. The verification results show that the minimum compensation accuracy of the sampling amplifier circuit with integrated dark current correction technology can reach 12 bit, the maximum compensation range can reach 500 mV, and the single column power consumption is only 1584 μW. At the same time, 1-4 times of gain amplification can be achieved, and the minimum gain step is 625%. The effect of dark current on the image quality and dynamic range of CMOS image sensor is eliminated from the analog front-end, which provides a theoretical support for high-end and high performance CMOS image sensor design.

    Jan. 01, 1900
  • Vol. 53 Issue 3 451 (2023)
  • WANG Xu, LIU Tao, and DENG Minming

    In order to meet the demands of areo-space electronic system for high speed high precision ADC, a radiation hardened 16-bit 80 MSPS ADC was designed. The core of 16 bit ADC was implemented with “3+4+3+3+3+3+3” pipelined structure, and the front dedicated buffer was used to reduce the kickback and improved the whole linearity of ADC. The radiation hardened technologies, such as edgeless MOS device and N+/P+ rings, were also exploited. The ADC was designed with standard 018 μm CMOS process. With the supply voltage of 33 V and 18 V, the clock frequency of 80 MHz and input frequency of 361 MHz, the power dissipation is less than 11 W, SNR is larger than 738 dB, and SFDR is larger than 88 dBFS, respectively. The SNR degrades less than 03 dB and SFDR degrades less than 1 dB after total ionizing dose irradiation of 150 krad(Si).The current increases less than 4 mA under Bi heavy ion irradiation.

    Jan. 01, 1900
  • Vol. 53 Issue 3 458 (2023)
  • WANG Zhikuan, FENG Zhihua, CHEN Rong, YAN Zipeng, CUI Wei, LU Ke, and LIAO Xiyi

    Compared with Si material, SiC material is widely used in high frequency and high power applications with high temperature resistance, high voltage resistance and high current resistance due to its superior material properties of large band gap, high thermal conductivity, high breakdown voltage and high electron saturation drift rate. Conventional wire bonding scheme has been one of the most preferred interconnection structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent in bonding wires. In this article, low parasitic inductance and high efficient cooling interconnection techniques for Si power modules are introduced first. Then, attempts on developing interconnection techniques for SiC power modules are thoroughly introduced. Finally, challenges in the interconnection of SiC power module are summarized.

    Jan. 01, 1900
  • Vol. 53 Issue 3 465 (2023)
  • RHONG Min, CHEN Xian, XU Xueliang, TANG Xinyue, ZHANG Zhengyuan, and ZHANG Peijian

    This paper comprehensively reviews the research progress on mechanical and electrical properties of silicon-based ultrathin flexible chips under uniaxial bending stress, including the bending test methods and the formulas for stress calculation, the bending stress induced effects on the responses of devices and cell circuits, as well as the device modelling strategies in considering bending stress effects. Bending stress can induce variations in critical electrical parameters such as mobility, threshold voltage and drain current of MOSFET, and the variation rate is closely related to the magnitude and direction of the applied stress. By combining the mathematical relations of varied electrical parameters and stress with the conventional device models, the new compact models suitable for flexible and bendable devices can be obtained, which enable the next generation computer-aided-design tools to meet the design needs of high-performance flexible chips in the future.

    Jan. 01, 1900
  • Vol. 53 Issue 3 472 (2023)
  • DU Haoyu, TAN Baimei, WANG Xiaolong, WANG Fangyuan, and WANG Ge

    Cobalt (Co) has advantages such as low electrical resistivity, good thermal stability, and strong adhesion to copper (Cu), which makes it a new barrier layer material that can replace tantalum (Ta) for copper interconnect structures in integrated circuits (ICs) with technology nodes below 14 nm. Chemical mechanical polishing (CMP) is the only method that can achieve both local and global planarization of copper interconnects, and it is also a key technology that determines the reliability of cobalt-based copper interconnect ICs. Citric acid contains hydroxyl groups that have a strong chelating effect on metal ions after ionization, and has become the main complexing agent in CMP and post cleaning of cobalt-based copper interconnect. The application and research progress of citric acid in copper interconnect CMP and post cleaning are reviewed in this paper, including the effect of citric acid on Cu/Co removal rate (RR) selectivity, the surface morphology of Co and the removal of residue on the Co surface in post Co CMP cleaning. The development trend of complexing agent and barrier layer CMP of copper interconnection is prospected.

    Jan. 01, 1900
  • Vol. 53 Issue 3 483 (2023)
  • YAO Yuhao, and JIANG Mei

    The successive approximation analog-to-digital converter (SAR ADC) has become the preferred architecture of ADC in low power digital-analog hybrid integrated circuit. As the core module, the power of high performance comparator directly determines the overall power dissipation of SAR ADC. Starting from the low power SAR ADC system, this work focused on the development histories and latest research progresses of high performance low power voltage and time domain comparators, and summarized the techniques of realizing low power comparator by optimizing SAR logic. This work could help mixed-signal circuit designers understand the new techniques of low power comparator in SAR ADC.

    Jan. 01, 1900
  • Vol. 53 Issue 3 492 (2023)
  • HAN Weimin, LIU Jiao, WANG Lei, HONG Ming, ZHU Kunfeng, and ZHANG Guangsheng

    A Spice sub-circuit macro model for annular gate LDMOS is presented. The macro model divided the annular gate LDMOS into two parts based on its structure. The middle part of annular gate LDMOS was a conventional LDMOS transistor whit rectangle gate. The terminal part was an annular gate LDMOS, and it was modeled individually. The macro model was verified by the N channel LDMOS in a 40 V BCD process. The results show that the macro model has good ability of geometry scaling and it can fit the characteristics curves of different size devices exactly. The macro model is compatible with commercial circuit simulator Hspice and Spectre.

    Jan. 01, 1900
  • Vol. 53 Issue 3 500 (2023)
  • NING Chaodong, ZHAN Yongxin, WU Qiannan, WANG Junqiang, and LI Mengwei

    Since the single-pole multi-throw switch (SPMT) needs to meet the performance requirements of broadband and high isolation when it is used to switch filters and transmission lines in phased array radars and bandwidth transceivers, a broadband and high isolation MEMS single-pole three throw switch (SP3T) was designed. The MEMS SP3T switch was optimized by using the HFSS module in ANSYS electromagnetic simulation software, and the mechanical properties of the upper electrode were simulated by COMSOL software. The simulation results show that the designed MEMS SP3T switch can work in the frequency band of 1-90 GHz. The insertion loss is less than 1 dB@90 GHz, the isolation is greater than 35 dB@90 GHz, and the overall volume is about 075 mm3.

    Jan. 01, 1900
  • Vol. 53 Issue 3 506 (2023)
  • LIANG Tao, XIAO Tian, LIU Yong, PEI Ying, HU Jingying, and RAN Wei

    Transient voltage suppressor (TVS) is an interface protection device in the form of a diode, in which a low-voltage TVS is usually composed of a low-resistance epitaxy and a high-concentration doped region on its surface. During the chip manufacturing process, the surface doping concentration of the wafer has a great influence on the device characteristics, and abnormal impurity diffusion changes can easily lead to abnormal device parameters. This paper investigates and confirms the abnormal parameters in the manufacturing process of a low-voltage TVS. It is confirmed that the abnormality is caused by the high surface doping concentration, and the trends of the surface doping concentration and device parameters are analyzed and verified by experiments.

    Jan. 01, 1900
  • Vol. 53 Issue 3 512 (2023)
  • CAI Zhikuang, YANG Hang, GU Peng, GUO Jingjing, WANG Zixuan, and GUO Yufeng

    With the continuous evolution of manufacturing process and the continuous increase of circuit scale, integrated circuits have gradually entered the post-Moore era. How to accurately and quickly extract parasitic capacitance parameters becomes more and more important to ensure design quality, reduce cost and shorten design cycle. In this paper, a two-dimensional capacitance extraction technology based on the segmented reservation method is proposed. The technique was based on an improved finite difference method, which used non-uniform meshing and solved asymmetric coefficient matrix equations to simulate the cross-section of interconnect structures. The proposed method could efficiently calculate the total capacitance per unit length of the main conductor and the coupling sum capacitance per unit length between the main conductor and adjacent conductors. A series of verification experiments had been completed. The experimental results show that the proposed two-dimensional capacitance extraction technology for interconnects can improve the calculation accuracy of parasitic capacitance by an average of 140 times and shorten the running time by an average of 10 %.

    Jan. 01, 1900
  • Vol. 53 Issue 3 518 (2023)
  • WAN Kai, GAO Jie, and NIU Rui

    Phototransistor is an important part of photo-electricity encoder circuit for spacecraft, which is sensitive to the displacement damage caused by high energy proton. Relationship between output current which is a key parameter for phototransistor and proton energy, displacement damage dose, working state and shielding materials was studied by irradiation test in this paper. With displacement damage dose increasing by 50, 60, 70, 92 MeV proton, the output current of phototransistor decreased almost 80%. It was caused by the initial photocurrent decreased in photodiode and the gain decreased in transistor. Stainless and sandwich shielding structure have almost no shielding effect on 60 MeV energy protons. The effect of displacement damage can be reduced by increasing the initial photocurrent or optimizing the photodiode to PIN type diode which can increase the depletion area.

    Jan. 01, 1900
  • Vol. 53 Issue 3 525 (2023)
  • FAN Yuandong, LI Hui, WANG Yingming, GAO Pengcheng, WANG Lei, and GAO Fei

    The surface morphology and quality of 150 mm SiC wafers cut by multi-wire diamond wire saw was analyzed. The surface roughness Ra of C-plane was about twice of the Si-plane by testing the surface roughness of both sides of SiC wafers, respectively. The Si-plane of wafer cut by lateral abrasive particles of multi-wire diamond wire saw was smoother with more grinding effect applied to this plane because of the wafer bending towards to the Si-plane. In addition, the damage layer depth on both sides of SiC wafer was measured by the bonded interface sectioning technique. The results show that the damage layer depth of the Si-plane is about 789 μm, significantly lower than 138 μm of the C-plane. Observed by microscope, the cross-section of Si-plane edge wafer is smoother. It is further proved that the grinding effect of lateral abrasive particles on the Si-plane is stronger due to the wafer bending, resulting in differences in surface morphology and quality on both sides of the SiC wafer.

    Jan. 01, 1900
  • Vol. 53 Issue 3 531 (2023)
  • WANG Peng, XU Qing, ZHANG Zhanhao, WANG Zebin, and JIN Zhiwei

    To address the problems of low detection accuracy and small detection area of the traditional Ring Oscillator (RO), a structure-optimized RO is proposed by improving the structure of the traditional RO, which improves the Trojan detection rate and detection area by increasing the contact area with the Trojan circuit. The experimental results on FPGA show that, compared with the traditional RO detection method, the structure-optimized RO has the following advantages The experimental results on FPGA show that the structure-optimized RO has the following advantages over the traditional RO detection method: 1) it can accurately detect a hardware Trojan with only 20 logic cells; 2) it expands the detection area of RO by about one time.

    Jan. 01, 1900
  • Vol. 53 Issue 3 536 (2023)
  • XIONG Huabing, LUO Chi, LI Jinlong, JIANG Kai, LI Shuangjiang, YIN Chao, and TAO Huailiang

    The main problem of eutectic die attach in military ceramics or metal packaging is that Sn based solder is easily oxidized to form Sn2O, SnO2 and other oxides, which will be constantly accumulated on the solder surface in the chip eutectic die attach process, forming the surface suspended particles of the solder, resulting in PIND failure. Based on the oxide film rupture theory, this paper realizes the high-purity nitrogen protection environment by improving the structure of eutectic sintered nitrogen protection currently used, and adopting a small semi-closed cavity. In the eutectic die attach process, the oxide film rupture was integrated into the solder body, and the molten solder that flowed out due to the oxide film rupture formed a new bright and rounded solder surface in good nitrogen protection environment, effectively reducing the suspended oxide particles on the solder surface. A large number of statistical data show that the improved study effectively reduces the PIND failure rate and the cost loss of the finished circuit. On the other hand, it was realized that very few suspended oxide particles were generated on the surface of the eutectic solder, which greatly reduced the hazard and reliability risk of short and open circuit and other malfunctions caused by movable particles.

    Jan. 01, 1900
  • Vol. 53 Issue 3 542 (2023)
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