Following a series of major breakthroughs in magnetic tunnel junction (MTJ) device architecture and materials^[1−3], spin transfer torque magnetic random access memory (STT-MRAM) has emerged as a leading candidate to replace eFlash in a variety of application scenarios, such as wearables, IoT, AI, and so on^[4−7]. Since its first successful commercialization in 2019, STT-MRAM keeps gaining significant momentum and capturing the high performance microcontroller (MCU) and system on chip (SoC) market with advanced embedded non-volatile memory solutions due to its high endurance, low power consumption as well as fast write operation^{[8, 9]}. Recently, leading foundries are on the process of qualifying STT-MRAM technology for automotive grade-0 applications (−40–150 °C) and strategically planning to launch next generation auto-grade MRAM memory products in the upcoming year^{[10, 11]}.

MRAMs used in these applications are primarily to solve the scaling and reliability issues of eFlash memory at advanced technology nodes. However, to fully address the need for high performance MCU applications, and to meet the growing demand for frequent data collecting and/or over-the-air updates, there has been a surge of interest in the development of fast-write, high-endurance non-volatile RAM (nvRAM)^{[12, 13]}.

In this paper, we demonstrate the functionality and reliability of an embedded 4 Mb MRAM (eMRAM) chip integrated onto a 40 nm CMOS platform in 300 mm wafers. We investigated the MTJ device read/write characteristics associated with sub-1 ppm error rate. The chip level MTJ reliability of endurance and retention was further verified. Through MTJ stack materials and process development, array yield of above 95% without repair and error correction code (ECC) was achieved and at the same time the product operation temperature was extended up to −40 to 125 °C with superior endurance performance at write speed of 20 ns. This substantially reduced sub-1 ppm bit error rate (BER) and reliability failures provides synergy in suppressing chip failure rate and thus enabling MRAM based nvRAM for high performance MCU applications.

Fig. 1(a) shows the 4 Mb eMRAM chip layout on a 40 nm CMOS platform. Each of the 4 Mb chips consists of 4 × 1 Mb sub-arrays. The main modules of the chip design, such as I/O, SA (sense amplifier), writer driver, etc., are illustrated in Fig. 1(a). The key storage MTJ device is highly compatible with the CMOS back-end-of-line (BEoL) process with only 4 masks added. Fig. 1(b) shows the cross-sectional TEM of MTJ arrays embedded in between metal layers of M4 and M5. The critical dimension (CD) of MTJ storage element was varied in the range of 60 to 90 nm and the MTJ stack was composed of seed layer/AP1 (antiparallel layer 1)/spacer/AP2 (antiparallel layer 2)/transition layer/reference layer/tunnel barrier/free layer/capping as illustrated in Fig. 1(c).

The MTJ film stacks of Ru/[Co/Pt]_×6/Ir/[Co/Pt]_×2/Mo/CoFeB/MgO/CoFeB/Capping were deposited on a smooth bottom electrode (BE) and subsequently patterned with special ion-beam etch (IBE) technique. The key structure of MTJ device consists of a tunnel barrier MgO layer sandwiched between a free layer with CoFeB and a fixed layer of Co/Pt superlattices. The fixed layer is employed with a synthetic antiferromagnetic (SAF) coupling scheme to strengthen the pinning field as well as to reduce the stray field^[14]. As the magnetization of the free layer rotates, the resistance state drastically changes due to tunneling magnetoresistance (TMR) effect^[15]. Here, TMR = (R_AP − R_P)/R_P, where R_P is parallel (P) and R_AP is anti-parallel (AP) state resistances.

In order to realize eMRAM based nvRAM mass production in high performance MCU, the raw BER that mainly originated from MTJ short/open hard failures as well as read/write random soft failures is required to be minimized. Through our conventional MTJ device process, using sub-1 ppm bit error rate standard, the array yield could only reach in the range of 0 to 20%. Through the failure analysis of read/write shmoo and accordingly via MTJ stack and process engineering, the sub-1 ppm array yield across 300 mm wafers was greatly improved.

Fig. 2(a) shows the MTJ R_P and R_AP distributions in the representative test key structure across wafer. As can be seen from Fig. 2(a), the R_P and R_AP distribution has been significantly tightened with MTJ stack B compared to that with MTJ stack A; correspondingly, the R_P variation within array (denoted as R_P_CV) showed around 4.47%, and 5.66% with MTJ stack B, and stack A, respectively. Moreover, the R_AP of MTJ stack B shifted right with a favorable larger TMR, reaching up to ~183% as compared to ~164% with MTJ stack A. The values of TMR over R_P_CV (TMR/R_P_CV) are commonly used to represent the read margin regarding the gap changes in the low and high resistance states. The larger the TMR/R_P_CV value, the smaller the read error rate [Sense amplifier (SA) requirement is above ~20]^[9]. As shown in Fig. 2(b), through MTJ stack engineering, the TMR/R_P_CV was enlarged from around 30 to 39 on average at room temperature (RT), leading to a significant improvement of the read window.

Fig. 3(a) compares the MTJ device resistance versus magnetic field (RH) loop characteristics. Each loop is obtained on an averaged 10 k sub-array MTJ devices. As shown in Fig. 3(a), the SAF stability has been substantially strengthened with MTJ process Ⅱ as compared to that with MTJ process Ⅰ. The single bit RH abnormality has been effectively eliminated, indicating that negligible reference layer switching under magnetic field of 6000 Oe. The respective device level write error rate (WER) of MTJ process Ⅰ and Ⅱ is also presented in Fig. 3(b). Although MTJ process Ⅱ showed about comparable WER characteristics, the write current as well as switching current distribution was significantly reduced by ~7% as compared to that of MTJ process Ⅰ. As a result, MTJ process Ⅱ effectively suppresses the read and write soft failures at the target bias condition, playing a crucial role in the sub-1 ppm yield improvement.

Therefore, by enhancing the MTJ device TMR ratio, tightening in-chip R_P and R_AP distribution, suppressing the unfavorable tail bits as well as switching current variations through novel stack materials and process engineering, the array yield at sub-1 ppm level across wafer was greatly improved from 0 to above 95% without repair and error correction code (ECC) enabled as shown in Fig. 4. Both the MTJ stack materials and process engineering contribute to the yield improvement. The sub-1 ppm array yield was significantly enhanced from around 0−20% to 60%−80% through MTJ stack materials innovation and it was further boosted up to around 95% and above with MTJ process engineering, as illustrated in Fig. 2 and Fig. 3, respectively. Furthermore, with the co-optimization of MTJ circuit design, especially the sense amplifier (SA) scheme of high temperature current leakage compensation, we achieve a sufficient read window with bit error rate (BER) <1 ppm across temperature from −40 to 125 °C as demonstrated in the read shmoo plot of Fig. 5, which guarantees the stable read operation at wide temperature range.

We perform chip level reliability characterization with our pilot line facilities. Fig. 6(a) shows the endurance progress with MTJ stack engineering as well as MTJ design. As can be seen from Fig. 6(a), the MTJ endurance has been drastically improved from about 1 × 10⁷ to 1 × 10¹² cycles with MTJ stack process tuning without the tradeoff of data retention performance.

The improvement of endurance performance could be ascribed to three major contributors. Firstly, the reduction of MTJ device write current as well as the tightening of switching current distribution as partly illustrated in Fig. 3(b) through MTJ materials innovation. Secondly, the increase of MTJ barrier breakdown voltage via MTJ barrier process tuning as shown in Fig. 6(b). Compared to barrier process Ⅰ, the barrier process Ⅱ boosts the MTJ barrier breakdown voltage more than 10%, resulting in around 2 to 3 orders increase of endurance at the targeted bias condition. The increase in breakdown voltage is thought to be attributed to the improved MgO barrier layer quality. Lastly but not least, the MRAM write circuit design innovation, e.g., array near and far end compensation, plays an effective role to boost up the endurance level to a next level, as illustrated in Fig. 6(a).

According to power law acceleration model, the time-to-failure (TTF) t under accelerated voltage (V_acc) conditions follows ln(t) = −nln(V_acc) + C, here C is a constant and n is an acceleration factor. By fitting the three accelerated tested voltage V_acc (1.224, 1.242, 1.264) and its corresponding endurance cycles of 7.29 × 10³, 2.07 × 10³, 6.97 × 10², as shown in Fig. 7(b), the acceleration factor n could be extracted. By employing equation t_op/t_acc = (V_op/V_acc)⁻ⁿ, the t_op or endurance cycles at given operation voltage (V_op) condition could be obtained by extrapolating the experimentally determined values. Finally, the endurance cycles as well as thermal stability (Δ) at target sub-1 ppm BER in the 4 Mb eMRAM chip across wafer were demonstrated as shown in Figs. 7(a) and 7(b). The estimated data retention could reach 10 years at 125 °C with over 148 dies evaluated across wafer and the estimated endurance cycle is around 1.1 × 10¹² cycle at the operating voltage (V_op) with the power law model. Take note this superior endurance and retention performance has been realized at a fast write speed of only 20 ns, which outperforms the macro performance to some extent in the recently reported literatures as compared in Table 1 below. Beyond that, the sub-1 ppm array yield without repair and ECC is prominent as compared to the previous report, thanks to the novel MTJ stack engineering and co-optimization of MTJ read/write circuit design.

For the high performance MCU applications, the magnetic immunity is of particular importance for MRAM. We have conducted magnetic immunity test for the package parts of 4 Mb chip under varying magnetic field (continuous exposure for over 1 min) and incidence of angle (90^o: incidence normal to the chip surface). The retention failure rate (ppm) for the worst case scenario is shown in Fig. 8 below.

As can be seen from Fig. 8, under external magnetic field applied up to around 650 Oe, the package parts retention failure could still remain as low as 0 ppm for varying angle of incidence. It demonstrated that our STT-MRAM chips could operate without error for unintended exposure to magnetic fields up to a few hundreds of Oe during installation, which is sufficient for most uses in the industrial or automotive applications^[17].

In summary, we presented a MRAM based nvRAM fabricated on a 300 mm wafer with 20 ns fast read/write speed, robust reliability and high yielding. Through advanced MTJ stack engineering, we have achieved sub-1 ppm array yield up to above 95% without repair and ECC. Innovations in MTJ materials, process and circuit design further allowed us to enhance the operating temperature and 10 years data retention up to 125 °C. Together with the high attainable endurance of over 1 × 10¹² expands the market prospects of embedded nvRAM products for high-performance industrial as well as Auto-G1 automotive MCU applications.