Light detection and ranging (LiDAR) systems based on direct time-of-flight measurements are essential for many applications that require three-dimensional information about objects, such as augmented reality/virtual reality (AR/VR), advanced driver-assistance systems (ADAS), and facial recognition^[1−3]. A typical direct time-of-flight light detection and ranging (LiDAR) system is shown in Fig. 1. High-sensitivity pixels consisting of SPADs and quenching circuits detect photons and generate electrical pulses, which will trigger timing circuits to record the photons' round-trip traveling time. After multiple detections, a histogram is constructed based on the time-correlated single photon counting (TCSPC) technique to obtain the probability distribution function of the photons over the detection period.

A high-performance timing circuit with high temporal resolution and low nonlinearity is required to construct the histogram without distortion. Historically, there are two main implementations of timing circuits: a time-to-digital converter (TDC)^[4] or a time-to-analog converter (TAC)^[5], followed by an analog-to-digital converter (ADC). For arrayed LiDAR sensors, multiple timing circuits are implemented simultaneously, either as pixel-level timing circuits or column-parallel timing circuits. The area and power consumption of one timing circuit are limited. Ring oscillator (RO)-based TDC has the advantage of compact structure and is popularly used in the realization of arrayed TDCs. The performance of RO is critical to RO-based TDC. In order to achieve a resolution of tens of picoseconds, the oscillator frequency or stages of the RO needs to be increased, resulting in an increment in power consumption. In addition, the phase noise of the open-loop RO will accumulate into time jitter, resulting in a decrement in the single-shot precision of ranging^[6].

Compared to TDC, TAC can realize better performance in terms of linearity with a large integration capacitor and resolution with an additional high-performance analog-to-digital converter (ADC)^[7]. However, large integrating capacitance is difficult to implement in array applications, and subsequent ADC implementation will bring additional costs. One solution is to use an operational transconductance amplifier (OTA) buffer with a large driving capability to output the voltage off-chip for AD conversion^[8]. A high-bandwidth and low-noise OTA is required to ensure transmission speed and linearity, which will bring additional power consumption. Another approach is to use an on-chip ADC for conversion. Ref. [9] used a column-shared 2-bit flash ADC for fast conversion at the expense of conversion resolution loss.

In high-speed and low-power analog-to-digital conversion applications, hybrid voltage/time domain ADC can be realized by combining TAC (sometimes also written as time-to-voltage converter, TVC) with successive approximation (SAR) ADC to convert the time-domain signal output by voltage-to-time converter (VTC)^{[10, 11]}. We have used a similar approach and proposed the column-parallel TA-ADC that merges the TAC and SAR ADC by sharing their capacitors. TA-ADC can continuously realize the function of time-to-analog and 12-bit analog-to-digital conversion without occupying too much area, which helps to achieve high temporal resolution and high frame rate at the same time.

This paper proposes a 128 × 128 SPAD LiDAR sensor with column-parallel TA-ADCs and a flash LiDAR system based on it. The paper is organized as follows: Section 2 provides an overview of the 128 × 128 SPAD sensor architecture and design details. Section 3 characterizes the sensor's measurement results, and Section 4 concludes this work.

The block diagram of the SPAD sensor is shown in Fig. 2. The sensor adopts a column-parallel readout architecture. The pixel array consists of 128 × 128 SPADs and front-end quenching circuits. Pixels in the same column share a tri-state bus to read out signals in a multiplexed manner. The pixel array works in a rolling exposure mode, enabling one row of pixels at a time, with odd columns of pixels connected to the TA-ADCs below the pixel array and even columns of pixels connected to the TA-ADCs above the pixel array. When the TA-ADC arrays finish the conversion, the data of TA-ADCs is read out simultaneously from the upper and lower sides of the chip through the parallel input-to-serial output (PISO). Reading out from both sides of the chip can use more input-ouput (IO) pads to transmit data, thereby increasing the data transmission speed.

The TA-ADC integrates a high-linearity TAC for converting the time interval into analog voltage and an SAR ADC for converting the analog voltage into digital output. The output of the TA-ADC is 13-bit, where the most significant bit (MSB) represents whether the signal is detected, and the lower 12 bits are the quantized output of the SAR ADC. By accumulating the most significant bit, the grayscale information can be obtained at the same time. On-chip digital control allows input parameter configuration to precisely adjust system exposure time and frame rate. Analog configuration drivers provide power supply and bias voltage distribution networks. Decoupling capacitors (Dcaps) are used to filter noise.

The top and bottom PISO arrays read out the data from the TA-ADC arrays. As shown in Fig. 3, every 16 TA-ADCs share a PISO. The sensor is exposed and read out by pipeline operation, and up to 25 kHz inter-frame rate can be achieved when operating at a typical 80 MHz clock frequency.

The pixel array structure builds upon our existing architectures^[12]. The SPAD used in the pixel is a P+/N-well diode, using polysilicon as a virtual guard ring to avoid interface noise caused by shallow trench isolation (STI). The diode is surrounded by a P-well to reduce the fringe electric field, and the device structure is compatible with standard CMOS processes. The details of the SPAD and its front-end quenching circuit are shown in Fig. 4. NM1 is used as a passive quenching resistor, and its resistance is adjusted by V_G. SEL and RST are used to externally gate and reset the pixel. The sensor adopts the single-event mode, that is, for each exposure, TA-ADC only records the time information of the first event. Therefore, V_G is set to 0 V, and the SPAD works in the parasitic capacitance quenching-external reset mode to reduce power consumption.

The timing diagram of the pixel operation is shown in Fig. 5. When the enable signal SEL is low, the anode of the SPAD is pulled up to V_QH, bringing the reverse bias voltage below the breakdown voltage (V_br). At the same time, the output of the three-state buffer is in the high impedance state. When both SEL and RST are high, the SPAD is reversely biased above V_br with an excess voltage of V_ex. After which, if a photon is detected, the SPAD will break down, and the avalanche current will charge the parasitic capacitor C_c, causing its voltage to rise rapidly and the SPAD to be quickly quenched. The voltage of the SPAD anode is read out through an inverter and a three-state buffer. The SPAD will remain quenched until the next SEL and RST pulses arrive. The pixel array works in a gated rolling exposure mode through the above method. The size of one pixel is 30 × 30 μm², and the fill factor of SPAD is 10%.

TAC can realize high-resolution time measurement, but its output voltage needs to be converted from analog to digital, usually with a single-slope ADC or an off-chip ADC. However, it is difficult for a single-slope ADC to achieve a high bit width and high conversion rate at the same time. Reading the voltage to off-chip requires a buffer with large drive capability, and the readout speed is limited. Another feasible way is to use the on-chip SAR ADC for fast conversion, but the DAC capacitor array occupies a large area. To reduce the area occupation, we propose the TA-ADC circuit that merges TAC and ADC through sharing capacitors while avoiding using the TAC output buffer.

Fig. 6 shows the proposed prototype of the TA-ADC. A differential structure is used to reduce common mode noise. The operating principle of the TAC period is to convert time to the voltage change on the capacitor by charging/discharging it. Subsequently, the voltage is quantized by successive approximation, and a 12-bit quantized output is obtained. Both TAC and ADC operations require large capacitors; therefore, sharing capacitors can simplify the circuit. Considering the discharging path of the TAC including a current source ($I$) with the output resistance ($r_{\text{o}}$) and an integrating capacitor ($C$), the voltage on the capacitor of the integration time ($t_{\text{i}}$) is given as:

1$V_{\text{C}}\left(t_{\text{i}}\right)=V_0{\text{e}}^{\frac{-t_{\text{i}}}{r_{\text{o}}C}}-\left(1-{\text{e}}^{\frac{-t_{\text{i}}}{r_{\text{o}}C}}\right)r_{\text{o}}I\mathrm{,}$

where $V_0$ is the initial capacitor voltage. The linearity of the TAC operation is impacted by the time constant ($r_{\text{o}}C$), if the time constant is significantly higher than the integration time, a first-order approximation of the expression is given as:

2$V_{\text{C}}\left(t_{\text{i}}\right)\approx V_0-\left(\frac{V_0}{r_{\text{o}}C}+\frac{I}{C}\right)t_{\text{i}}\mathrm{.}$

A cascade current source with differential current switches is adopted to improve the $r_{\text{o}}$. In order to improve the voltage margin, the current source uses high-voltage transistors. Transistors NM1 and PM1 are used to reset the two capacitor arrays to 0 and 1.8 V, respectively, before time-to-voltage conversion. During the time-to-voltage conversion, the switches PM3 and NM3 are turned on, and the two capacitor arrays are used as integrators, which, together with the current source, form a TAC circuit. After the time-voltage conversion, the switches PM3 and NM3 are turned off, and PM2 and NM2 are turned on. The current source is disconnected from the capacitors. Then, in the ADC period, the capacitor arrays act as the DAC capacitors of the ADC, and the 12-bit ADC quantifies the integrated voltages on the capacitors by successive approximation and finally obtains high-resolution conversion results. The unit capacitance of the DAC array is 1 fF, and the total DAC capacitor is about 2 pF. With the structure of the shared capacitor, the integration capacitor of the TAC period is up to 2 pF without occupying an additional area. Thus, a large RC constant can be obtained, increasing the linearity of the time measurement.

The length of the transistors in the current source is appropriately increased to 1.6 μm to reduce 1/f noise and increase output impedance. Assuming the output impedance $r_{\text{o}}$ of the cascade current source is high enough, the Eq. (2) can be simplified as:

3$V_{\text{C}}\left(t_{\text{i}}\right)\approx V_0-\frac{I}{C}{t}_{\text{i}}\mathrm{.}$

Thus, the convert gain of the differential TAC is:

4$\frac{\text{d}{V}_{\text{d}}}{\text{d}{t}_{\text{i}}}=\frac{2I}{C}\mathrm{,}$

where $V_{\text{d}}$ is the differential output voltage of the TAC. The gain of the TAC can be adjusted by changing the current via RAN<1:0>. A current bias module is used to copy the off-chip bias current to the TA-ADC array. The current ratio between $I_{\text{bias}}$ and $I_{\text{TA}-\text{ADC}}$ is 400 : 64/48/32/16, which is controlled by RAN<1:0>. As shown in Fig. 7, a larger current can be selected to achieve higher temporal resolution for close-range applications and a smaller current can be selected to achieve a higher dynamic range for long-range applications. The TAC reset operation initializes the ADC's differential input to −1.8 V, and then the ADC's differential input grows linearly over integration time, meaning that the maximum input range of the ADC is −1.8 to 1.8 V. When the off-chip bias current is set to 450 μA, RAN is set to 2, and the corresponding current is 36 μA, the time resolution can be achieved as 25 ps.

The timing diagram of the TA-ADC is shown in Fig. 8. In a TCSPC-based system, the detection rate should be no more than 5% of the illumination rate to avoid pile-up distortion^[13]. This means that most exposures are useless and photons cannot be detected. In this case, turning on the TA-ADC normally will result in useless power consumption. Therefore, we adopted the reverse start-stop method to reduce power consumption. As shown in Fig. 8, a laser pulse is emitted at the rising edge of SEL and if the pixel detects a photon, the output of the pixel, POUT, turns high, thus enabling the TAC to charge the capacitors with a constant current until the SEL signal turns low, at which the TAC stops working and the ADC starts conversion on the next clock arrival. After 12 clock cycles, ADC completes the quantization and outputs 13-bit data, where the MSB is an identification bit, 1 for detecting photons, and 0 for no detection. Then the time of flight is given by

5$\text{TOF}=K\times \text{CLK}-\Delta t\mathrm{.}$

As shown in Fig. 8, the pulse width of SEL is $K\times \text{CLK}$. $K$ can be chosen from 1 to 31, and $\Delta t$ is the time interval from the rising edge of POUT to the falling edge of SEL.

In order to reduce the ADC's power consumption, AD_START can only be pulled high to generate the comparator's clock, CLKC, when POUT is high. Otherwise, no valid clock of the comparator will be generated, and the ADC will not work during invalid detection. In this way, the ADC's power consumption can be greatly reduced. Due to the shared capacitor structure, the TAC output buffer is avoided, and the area of the proposed TA-ADC is greatly reduced to 60 × 530 μm².

The chip has been fabricated with a standard 0.18 μm CMOS technology, and the micrograph and characteristics of the chip are shown in Fig. 9. Its dimensions are 5.2 × 6.2 mm². The details of the sensor measurement results are shown below.

A TOF system was built to demonstrate the sensor's range detection and imaging capability. A commercial 640 nm laser with a peak power of 4 mW and a full width at half maximum (FWHM) of 90 ps was used. A field programmable gate array (FPGA) was used to control both the sensor and the laser while preprocessing the output data of the sensor. Firstly, the whiteboard placed at different positions was measured, by moving the whiteboard at equal intervals of $\Delta X$, multiple measurement results were obtained, then the time resolution can be expressed as:

6$t_{\text{res}}=\frac{2\times \Delta X}{c\times \overline{\Delta N}}\mathrm{,}$

where $\overline{\Delta N}$ is the measured average increment between adjacent distances and $c$ is the speed of light. The measured average time resolution is 25.7 ps, which is consistent with the theoretical value of 25 ps. By measuring the whiteboard at different positions, the sensor's fixed system delay can be obtained and subtracted in subsequent experiments.

To measure the nonlinearity of the TA-ADC, a code density test was performed by triggering the pixel array to generate random events with dim ambient light. In order to avoid the effect of pile-up distortion, the number of expected events generated during each exposure needs to be much smaller than one, thus requiring a long time for the measurement. Due to the extremely large quantity of exposure and data used to construct the histogram, only the lower 9 bits of data were analyzed. The corresponding DNL/INL measured results are shown in Fig. 10, and the periodic error is caused by the capacitance mismatch of the ADC. The worst DNL (INL) was +0.30/−0.77 (+1.41/−2.20) LSB.

The depth linearity from 0.1 to 1 m was measured by a step of 5 cm, and twenty times measurements were taken for each distance to measure the depth accuracy (deviation between the measured average value and the true value) and single-shot precision (standard deviation of the measured value). As shown in Fig. 11, the worst depth precision and accuracy are 0.77 and 1.47 cm, respectively.

The imaging capabilities of the sensor were also tested, up to 25 kHz inter-frame rate can be achieved when operating at a typical 80 MHz clock frequency. The imaging scene consists of a plaster human body, a cuboid, and a white background board placed about 0.5 m in front of the lens. The gray information is obtained by summing the MSB of the 13-bit output data (an identification bit, 1 for detecting photons, and 0 for no detection). The 2D and 3D point cloud images are shown in Figs. 12(a) and 12(b), and median filtering with a neighborhood size of 2 × 2 is used to eliminate signal-independent noise.

Table 1 shows a comparison of the sensor with other SPAD flash LiDAR sensors. Our sensor achieves higher spatial resolution compared to other works. Due to the gated rolling exposure method and the reverse start-stop method of TA-ADC, the sensor power dissipation is only 190 mW. The image sensor in Ref. [8] uses an analog timing technique called TII with counters to extend the dynamic range, but quantization with off-chip ADCs limits the maximum inter-frame rate to only 8.3 kHz. Imager sensors in Refs. [2, 14] adopt delay line TDC and RO TDC, respectively, to achieve a larger timing depth but a lower timing resolution and higher nonlinearity. The image sensor in Ref. [14] achieves an inter-frame rate of 270 kHz, which is 10.8 times higher than our sensor, but the pixel number of ours is 16 times higher than it. To compare the energy efficiency of the sensors, Table 1 uses a figure-of-merit (FoM) for comparison^[15]. Our sensor achieves a FoM of 7.14 pJ/pixel.

This paper proposes a LiDAR sensor fabricated in 180 nm CMOS technology, integrating 128 × 128 SPADs, and 128 column-parallel TA-ADCs. Both 2D and 3D imaging can be obtained simultaneously at an inter-frame rate of 25 kHz. The proposed column-parallel TA-ADC achieves high time resolution and conversion rate at the same time by integrating TAC and SAR ADC in a compact layout through sharing capacitors, and compared with sensors using off-chip ADC, a higher inter-frame rate is realized.