Fig. 1. Exceptional optical characteristics of chalcogenide PCMs and their deposition processes at low temperatures. (a) Optical constants of GST at different states^[14]; (b) morphologies of low-loss Sb₂Se₃ fabricated via magnetron sputtering and thermal evaporation^[47]

Fig. 2. Integration schemes of all-optical in-memory computing device. (a) Schematic diagram of chalcogenide PCM-based hybrid optical waveguide^[73]; (b) multilevel switching results and the corresponding amorphization region of PCM; (c) programmable optical switch based on pixel switching^[36]

Fig. 3. Electron beam exposure based integrating scheme. (a) Structural diagram of electrically programmable in-memory computing device^［35］; (b) sub-micron-meter chalcogenide PCM-based optical switch^[75]; (c) plasmonic nanogap optical switch^[39]; (d) subwavelength optical switch^[60]; (e) subwavelength optical phase shifter^[76]

Fig. 4. Fabrication flowchart of monolithic back-end integration scheme^[46]

Fig. 5. Chalcogenide PCMs based integrated photonic devices configured by coupling optical pulses into waveguides. (a) Structural diagram of in-memory computing device^[31]; (b) twelve level states and (c) six repeatable levels realized using a series of laser pulses^[31]; (d)(e) separation of the island structure facilitates a more uniform distribution of light field, thereby decreasing loss and resonance^[33]; (f)(g) mode converter based on structured GST with varying size, achieving a programming resolution of 6 bit^[34]

Fig. 6. Chalcogenide PCM-based integrated photonic devices configured by coupling optical pulses into waveguides. (a) Initial 50 ns two-step programming pulse remains constant, while the alteration of the target state is achieved by adjusting the duration and power of the subsequent tail pulse^[28]; (b) schematic diagram illustrates the double-step programming pulse crystallization method^[28]; (c) utilization of PWM optical pulses to control photonic phase shifting devices integrated with chalcogenide PCMs on waveguides^[31]; (d) phase change memory using Sb^[86]; (e) schematic diagram of SST phase change memory^[90]; (f) amorphization (write) process utilizes pulses with a pulse width of 5 ns, enabling the achievement of nine distinct levels. On the other hand, crystallization (erase) employs pulses with a pulse width of 50 ns, allowing for ten different grades^[90]

Fig. 7. Related researches based on the method of focused laser pulses in the free space. (a) Schematic diagram of regulation of spatially focused laser pulses^[91]; (b) GST-assisted micro ring optical switch^[91]; (c) GSST-assisted micro ring optical switch^[26]; (d) transition from the crystalline to the amorphous phase takes place both prior to and subsequent to regulation^[26]

Fig. 8. Pixel switching by spatial light^［36］. (a) Initial state and mode field distribution of amorphous thin films; (b) crystallization of partial pixels leads to modification in the mode field distribution

Fig. 9. Rewritable photonic integrated devices based on chalcogenide PCMs^[95]. (a) Schematic diagram of laser direct writing; (b) procedure of writing, erasing, and overwriting a device; (c) process of rewriting the route

Fig. 10. Recently proposed electrically reconfigurable in-memory computing devices^{[35,39-40,53,60,62,75-77,95-107]}. Schemes of inducing phase change by self-heating: (a1) GST produces heat directly, (a2) GeTe produces heat directly, and (a3) GST produces heat directly in nanogap configuration; schemes of inducing phase change by metal microheater: (b1) aluminum-based microheater and (b2) gold-based microheater in nano gap architecture; schemes of inducing phase change by transparent microheater: (c1)-(c6) ITO-based transparent microheaters and (c7) In₂O₃-based transparent microheaters; schemes of inducing phase change by doped silicon microheaters: (d1)(d2) doped silicon-ITO hybrid microheaters, (d3) P++ doped silicon microheater and (d4) N++-I-N++ (NIN) doped silicon microheater; (e1)-(e5) P++-I-N++ (PIN) doped silicon microheaters

Fig. 11. Parallel optical networks for in-memory computing based on chalcogenide PCMs. (a) Programmable multimode computing core (PMMC)^[33]; (b) enhanced in-memory computing framework for Pavlovian association learning^[21]; (c) utilization of wavelength division multiplexing in-memory computing framework for acceleration of statistical analysis^[121]; (d) framework of phase-change in-memory computing utilizes the principle of rank-reduction matrix factorization^[122]; (e) scalable neural mimic computing system, which integrates micro ring resonators and Bragg grating structures, is successfully implemented to demonstrate a large-scale in-memory photonic computing network^[87]; (f) enhanced in-memory convolution kernels through the multiplexing of spatial, wavelength, and temporal dimensions^[22]

Fig. 12. Optical networks for electrically reconfigurable in-memory computing based on chalcogenide PCMs. (a) Architecture of the in-memory dot product computing engine^[105]; (b) in-memory dot product computing engine is utilized for the analysis of image brightness transformation and recognition of convolutional neural network for Fashion-MNIST dataset, with σ representing the standard deviation^[105]; (c) architecture of the partial differential equation solver based on a non-volatile tuning scheme^[123]; (d) results obtained from a partial differential equation solver to solve the heat diffusion equation of a spacecraft’s heat shield^[123]

Fig. 13. On-chip fast training compatible in-memory optical computing architecture^[30]