Fig. 1. Integration schemes for implementing wavelength matching in EML^[5]

Fig. 2. Schematic of EML structure

Fig. 3. Microscopic image of 4×25 Gbit/s EML array^[6]

Fig. 4. Schematic of EML+SOA chip^[10]

Fig. 5. Property of EML+SOA^[10]. (a) Driving method; (b) optical power versus power consumption

Fig. 6. Schematic of packaging structure of EML^[11]. (a) Wire interconnection; (b) flip-chip interconnection

Fig. 7. 107-Gbit/s eye diagrams for back-to-back, 2- and 10-km transmission^[11]

Fig. 8. Package diagram of EML array^[12]. (a) Wire interconnection; (b) flip-chip interconnection

Fig. 9. EML with on-chip matching circuit^[13]. (a) Microscopic image; (b) large signal modulation eye-diagram at 56 Gbit/s

Fig. 10. Double side EML based on identical epitaxial layer^[14]. (a) Schematic diagram; (b) microscopic image

Fig. 11. L band EML+SOA array^[15]. (a) Microscopic image; (b) eye-diagrams at 56 Gbit/s

Fig. 12. Schematic of EML chip based on identical epitaxial layer

Fig. 13. 40 Gbit/s large signal eye-diagram of EML emission module based on identical epitaxial layer^[20]

Fig. 14. Lasing spectra and eye-diagrams of O-band gain-coupled 4×25 Gbit/s EML array (with external SOA)^[21]. (a) Lasing spectra; (b) eye-diagrams