Journal of Electronic Science and Technology, Volume. 23, Issue 2, 100306(2025)

Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell

Mahamudul Hassan Fuad1,2、*, Md Faysal Nayan2, Sheikh Shahrier Noor2, Rahbaar Yeassin2, and Russel Reza Mahmud2、*
Author Affiliations
  • 1Department of Electrical and Electronic Engineering, Dhaka International University, Dhaka, 1212, Bangladesh
  • 2Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka, 1208, Bangladesh
  • show less
    References(44)

    [3] [3] S.K. Sinha, S. Chaudhury, Oxide thickness effect on quantum capacitance in singlegate MOSFET CNTFET devices, in: Proc. of Annual IEEE India Conf., Kochi, India, 2012, pp. 42–46.

    [5] [5] T.T. Zhang, P.I. Mak, M.I. Vai, P.U. Mak, F. Wan, R.P. Martins, An ultralowpower filtering technique f biomedical applications, in: Proc. of Annual Intl. Conf. of the IEEE Engineering in Medicine Biology Society, Boston, USA, 2011, pp. 1859–1862.

    [6] [6] A.Yalla, U.Na, Quasi FGMOS 6T SRAM cell design: a strategy f low power applications, Int. J. Nanosci., doi: 10.1142s0219581x20400049.

    [10] Nayak D., Rout P.K., Sahu S., Acharya D.P., Nanda U., Tripthy D.. A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption. high stability and performance, Microelectron. J., 97, 104723(2020).

    [12] Gupta R., Dasgupta S.. Process corners analysis of data retention voltage (DRV) for 6T, 8T, and 10T SRAM cells at 45 nm. IETE J. Res., 65, 114-119(2019).

    [14] [14] A. Javey, J. Guo, Q. Wang, M. Lundstrom, H.J. Dai, Ballistic carbon nanotube fieldeffect transists, Nature 424 (6949) (2003) 654–657.

    [16] [16] A. Pushkarna, S. Raghavan, H. Mahmoodi, Comparison of perfmance parameters of SRAM designs in 16 nm CMOS CNTFET technologies, in: Proc. of 23rd IEEE Intl. SOC Conf., Las Vegas, USA, 2010, pp. 339–342.

    [18] Valluria A., Musala S.. Comparative analysis of CNTFET based SRAM cells. ECS T., 107, 19177-19186(2022).

    [19] Rajendra Prasad S., Madhavi B.K., Lal Kishore K.. Design of low-leakage CNTFET SRAM cell at 32 nm technology using forced stack technique. International Journal of Engineering Research and Applications (IJERA), 2, 805-808(2012).

    [20] [20] M.H. Fuad, S.S. No, K.M. Mehedi Hassan, M. Rahman, H.A. Khatun Labony, F. Nayan, acterizing CNTFET logic gate adder perfmance tradeoffs by considering CNT tube diameter dielectric constant, in: Proc. of IEEE 9th Intl. Women in Engineering (WIE) Conf. on Electrical Computer Engineering, Thiruvananthapuram, India, 2023, pp. 206–211.

    [21] [21] M. Spasova, G. Angelov, B. Dobrichkov, E. Gadjeva, M. Hristov, DRAM design based on carbon nanotube field effect transists, in: Proc. of 2016 39th International Spring Seminar on Electronics Technology (ISSE), Pilsen, Czech Republic, 2016, pp. 372–377.

    [22] [22] F. Zaho, T.Z.A. Zulkifli, F.A. Khay, A.A. Fida, Lowpower RRAM device based 1T1R array design with CNTFET as access device, in: Proc. of 2019 IEEE Student Conference on Research Development (SCeD), Bar Seri Iskar, Malaysia, 2019, pp. 280–283.

    [23] [23] K.S. Novoselov, A.K. Geim, S.V. Mpzov, et al., Electric field effect in atomically thin carbon films, Science 306 (5696) (2004) 666–669.

    [24] [24] M.H. Fuad, F. Nayan, R. Yeassin, A. Raihan, S.S. No, R.R. Mahmud, Quantum insights into dielectric materials oxide thicknessdependent conductance in singlewalled CNTFET: a parametric simulation study, in: Proc. of Intl. Conf. on Advances in Computing, Communication, Electrical, Smart Systems, Dhaka, Bangladesh, 2024, pp. 1–6.

    [26] [26] J. Deng, Device Modeling Circuit Perfmance Evaluation f Nanoscale Devices: Silicon Technology beyond 45 nm Node Carbon Nanotube Field Effect Transists, Ph.D. dissertation, Stanfd University, Stanfd, USA, 2007.

    [27] [27] J. Deng, H.S.P. Wong, A compact SPICE model f carbonnanotube fieldeffect transists including nonidealities its application – part I: model of the intrinsic channel region, IEEE T. on Electron Dev. 54 (2007) 3186–3194.

    [28] [28] N.H.E. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, AddisonWesley Longman Publishing Co., Inc., Boston, USA, 1985.

    [30] Aura S.R., Ishraqul Huq S.M., Biswas S.N.. Design of high-speed dual port 8T SRAM cell with simultaneous and parallel READ-WRITE feature. IJECES, 13, 823-829(2022).

    [31] Elangovan M., Gunavathi K.. Effect of CNTFET parameters on novel high stable and low power: 8T CNTFET SRAM cell. T. Electr. Electro., 23, 272-287(2022).

    [34] Tan M.L.P., Lentaris G., Amaratunga G.. Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET. Nanoscale Res. Lett., 7, 467(2012).

    [37] Imam S.-A., of gate insulator thickness and diameter over on/off current ratio in ballistic CNTFETs Effects. Intl. J. of Adv. Res in Electrical. Electronics and Instr. Eng., 2, 5424-5429(2013).

    [38] [38] R. Djamil, B. Salima, L. Kheireddine, Numerical study perfmance analysis of carbone nanotube field effect transists, in: Proc. of 2013 36th International Convention on Infmation Communication Technology, Electronics Microelectronics (MIPRO), Opatija, Croatia, 2013, pp. 43–47.

    [39] Sankar P.A.G., Kumar K.U.. Design and analysis of low power. delay optimized digital buffer based on CNFET technology, International Journal of NanoScience and Nanotechnology, 4, 181-193(2013).

    [40] [40] A. Adlakha, W. Hussain, L.R. Solay, S.I. Amin, S. An, P. Kumar, Design analysis of 6T SRAM implementation upon dual gate junctionless FET, in: Proc. of 3rd Intl. Conf. on Intelligent Technologies, Hubli, India, 2023, pp. 1–6.

    [41] [41] P. Goel, M.G. Agrawal, S. An, P. Kumar, L.R. Solay, Design investigation of SRAM using ge plasma dopingless nanowire FET, in: Proc. of Wld Conf. on Communication & Computing, Raipur, India, 2023, pp. 1–8.

    [42] [42] Y. Kumar, A. Raman, R. Ranjan, R.K. Sarin, Highfrequency CNTFETbased voltagecontrolled oscillat f PLL application, in: D.K. Sharma, V.E. Balas, L.H. Son, R. Sharma, K. Cengiz (Eds.), MicroElectronics Telecommunication Engineering, Springer, Singape, 2020, pp. 413–419.

    [43] Rao M.V.N., Hema M., Raghutu R. et al. Design and development of efficient SRAM cell based on FinFET for low power memory applications. J. Electr. Comput. Eng., 2023, 7069746(2023).

    Tools

    Get Citation

    Copy Citation Text

    Mahamudul Hassan Fuad, Md Faysal Nayan, Sheikh Shahrier Noor, Rahbaar Yeassin, Russel Reza Mahmud. Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell[J]. Journal of Electronic Science and Technology, 2025, 23(2): 100306

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category:

    Received: Aug. 15, 2024

    Accepted: Feb. 26, 2025

    Published Online: Jun. 16, 2025

    The Author Email: Mahamudul Hassan Fuad (mahamudulhassan.eee@diu.ac), Russel Reza Mahmud (r.r.mahmud.eee@aust.edu)

    DOI:10.1016/j.jnlest.2025.100306

    Topics