Journal of Electronic Science and Technology, Volume. 23, Issue 2, 100306(2025)
Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell
Figures & Tables(16)
Fig. 4. Write delay and read delay vs different temperature of CMOS based 8T SRAM.
Fig. 8. Write delay vs tube diameter 8T CNTFET based SRAM with multiple tube positions.
Fig. 9. Read delay vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.
Fig. 10. Power consumption vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.
Fig. 11. Comparative analysis of CMOS and CNTFET based SRAM in terms of power consumption for different tube diameter and temperature analysis.
Fig. 12. Write PDP vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.
Fig. 13. Read PDP vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.
Table 1. Device parameter.
View tableView in ArticleTable 1. Device parameter.
Stimuli (Setup) Parameter RBL RWL WWL BL BLB VDD (DC) Voltage 1 0 V 0 V 0 V 0 V 1 V 1 V Voltage 2 1 V 1 V 1 V 1 V 0 V Period 30 ns 40 ns 30 ns 60 ns 60 ns Delay time 10 ps 10 ps 10 ps 10 ps 10 ps Rise time 10 ps 10 ps 10 ps 10 ps 10 ps Fall time 10 ps 10 ps 10 ps 10 ps 10 ps Pulse width 15 ns 20 ns 25 ns 30 ns 30 ns
Table 2. Device parameter definitions and default values [26,27].
View tableView in ArticleTable 2. Device parameter definitions and default values [26,27].
Specifications of device Detailed explanation of the parameters Default value Lch Channel length in physical terms. Additional quantum mechanical consequences need to be considered for channel lengths below 10 nm, when this reasoning may not hold. 32.0 nm Lgeff The (intrinsic) channel region has a mean uncontrolled path due to non-ideal flexible dispersion. 200.0 nm Lss The length of the source side development section (CNT) that was intentionally doped. 32.0 nm Ldd The distance between the doped CNT source region and the drain-side expansion zone. 32.0 nm Efi Fermi level within an altered source/drain tube. 0.6 eV Kgate Dielectric permittivity. 16.0 Tox Oxide thickness at the top gate (planer gate). 4.0 nm Csub The capacitance of interaction among the channel region along with the substrate (back gate). 20.0 pF/m Ccsd The capacitance of association within the channel’s interior region and source-drain region. 0.0 pF/m Couple ratio Coupling capacitance between the channel and discharge, represented as a share of Ccsd. 0.0
Table 3. Comparative analysis between different technologies SRAM.
View tableView in ArticleTable 3. Comparative analysis between different technologies SRAM.
Technology Write delay Read delay Power consumption PDP CNTFET (in this work) 4.94 ps 4.951 ps 1.971 nW 10.68 zJ FinFET [ 40 ,43 ]0.75 ns 2.85 ns 12.52 nW 4.53 nJ TFET [ 41 ,44 ]3.554 ns 2.292 ns 0.412 pW – CMOS (in this work) 41.2 ps 16.16 ps 13.7 nW 64.84 zJ
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Mahamudul Hassan Fuad, Md Faysal Nayan, Sheikh Shahrier Noor, Rahbaar Yeassin, Russel Reza Mahmud. Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell[J]. Journal of Electronic Science and Technology, 2025, 23(2): 100306
Paper Information
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Received: Aug. 15, 2024
Accepted: Feb. 26, 2025
Published Online: Jun. 16, 2025
The Author Email: Mahamudul Hassan Fuad (mahamudulhassan.eee@diu.ac), Russel Reza Mahmud (r.r.mahmud.eee@aust.edu)
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