The exponential growth of artificial intelligence (AI) large models, such as ChatGPT and DeepSeek, has catalyzed unprecedented demand for high-performance computing infrastructure. Projections indicate China’s intelligent computing power will reach 1037.3×10¹⁸ by 2025, with global private investments in AI infrastructure surpassing 2 trillion RMB in 2024. Traditional electrical interconnections, however, encounter fundamental limitations in power consumption and transmission distance (typically below several meters), proving inadequate for large-scale AI cluster expansion involving millions of accelerator processing units (XPUs). Optical interconnections present advantages in latency, transmission distance, and bandwidth density, positioning them as essential enablers for next-generation AI computing capabilities. Co-packaged optics (CPO) technology, which integrates high-density optical engines with switching chips or XPUs on a shared high-speed substrate, significantly reduces electrical signal paths and power consumption. Silicon photonic technology, compatible with complementary metal-oxide-semiconductor (CMOS) processes, enables monolithic integration of photonic and electronic devices, making silicon-based micro-ring optical engines central to CPO development due to their compact footprint, energy efficiency, and wavelength selectivity for wavelength division multiplexing (WDM).

Multi-wavelength lasers: These are essential for WDM-enabled high-density interconnects. Key solutions include distributed feedback (DFB) laser arrays, comb lasers, and mode-locked lasers. Ayar Labs’ 2024 16-channel SuperNova laser [Fig. 2(a)] complies with the CW-WDM MSA standard, delivering 200 GHz-spaced wavelengths with 2 dBm power at 55 ℃. Intel achieves 16 wavelengths with only 4 lasers via multi-period gratings [Fig. 2(b)], while Innolume’s quantum dot Fabry?Perot comb laser [Fig. 2(e)] supports 24 channels at 100 GHz spacing. The quantum dot mode-locked laser by Institute of Physics, Chinese Academy of Sciences [Fig. 2(f)] demonstrates 4-channel 100 Gbit/s transmission at 80 ℃.

Micro-ring modulators (MRMs): Compared to Mach?Zehnder modulators (MZMs), MRMs offer micron-scale size and low power consumption, ideal for CPO. Innovations in junction designs (lateral, L-shaped, vertical) have significantly improved performance. The lateral-junction MRM by Xi’an Institute of Optics and Precision Mechanics, Chinese Academy of Sciences [Fig. 3(d)] achieves >67 GHz bandwidth and 256 Gbit/s PAM4 transmission rate. TSMC’s 65 nm silicon photonics process enables MRMs with 76 GHz bandwidth and 0.35 V·cm efficiency (Table 2). Thermal tuning systems (Fig. 4) using resistive heaters and closed-loop feedback address wavelength drift from fabrication errors and temperature fluctuations, with ETH Zurich’s demonstration achieving 10 pm tuning precision [Fig. 4(d)].

Germanium (Ge)-on-silicon detectors overcome silicon’s transparency to infrared light. Huazhong University of Science and Technology’s U-shaped electrode vertical PIN detector [Fig. 5(b)] reaches 103 GHz bandwidth with 1.3 nA dark current. Germany’s IHP develops a fin-shaped lateral PIN detector [Fig. 5(c)] achieving 265 GHz bandwidth by optimizing carrier transport (Table 4).

Micro-ring filters enable compact WDM demultiplexing. The University of British Columbia demonstrates that second-order dual-ring filters surpass single rings in crosstalk (-15 dB) and channel count (31×50 GHz). Polarization-insensitive receivers [Fig. 6(a)] and polarization diversity structures [Fig. 6(b)] address random polarization in fiber links.

CMOS-driven MRMs reduce power consumption. Intel’s 28 nm driver with nonlinear equalization [Fig. 7(b)] supports 112 Gbit/s PAM4 with 5.8 pJ/bit efficiency. AMD’s 7 nm transimpedance amplifier (TIA) [Fig. 8(d)] achieves 0.96 pJ/bit (Table 6).

2.5D integration [Fig. 9(a)] employs interposers for high-density interconnects, while fan-out wafer-level packaging (FOWLP) [Fig. 9(b)] provides flexibility for CPO. 3D integration with through-silicon vias (TSVs) [Fig. 9(c)], as demonstrated by TSMC’s CoWoS process, targets 6.4 Tbit/s engines by 2026. Optical coupling technologies include IBM’s reflow-compatible polymer waveguide [Fig. 11(a)] and Intel’s pluggable glass waveguide connector [Fig. 11(b)], achieving <3 dB insertion loss.

Silicon-based micro-ring optical engines have demonstrated substantial progress, with components achieving performance requirements of 100?200 Gbit/s per channel. Several critical challenges persist: enhancing thermal tuning stability for multi-channel WDM, improving packaging yield in the presence of photonic process variations, and maintaining optical connector reliability under thermal stress. Future development trajectories include advancing single-channel speeds to 200 Gbit/s and optimizing compatibility with Universal Chiplet Interconnect Express (UCIe) interfaces. The standardization initiatives led by OIF and COBO remain essential for addressing protocol fragmentation. Given the continued advancement in integration density, power efficiency, and manufacturing scalability, micro-ring-based CPO demonstrates significant potential to enhance next-generation artificial intelligence and high-performance computing infrastructure.