Journal of Semiconductors, Volume. 45, Issue 6, 062203(2024)
An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump
Figures & Tables(19)
Fig. 1. (Color online) The structure of prior technology. (a) Adaptive biasing and (b) event-driven charge pump.
Fig. 2. (Color online) (a) Conceptual circuit diagram of the traditional NMOS OCL-LDO with a CP loop and (b) trade-offs among IG, tD, and the regulation dead.
Fig. 3. (Color online) The circuit architecture of the proposed OCL-LDO.
Fig. 4. (Color online) (a) Schematic of CP with the proposed DSC and (b) the operation of DSC.
Fig. 5. (Color online) The PVT simulation of load transient response of the proposed OCL-LDO under different VBAT.
Fig. 6. (Color online) Simulated essential waveforms for different cases: (a) without CP, (b) with CP but without DSC, and (c) with proposed DSC-CP.
Fig. 7. (Color online) The structure of the low-power current-based transient detection circuit and operation principle of different cases: (a) undershoot and (b) overshoot.
Fig. 8. (Color online) The schematic of (a) inner voltage regulator, and (b) area-efficient current source charge pump.
Fig. 9. (Color online) (a) The schematic of the proposed dynamic EA and (b) the equivalent circuit under transient variations.
Fig. 10. (Color online) Small-signal model for stability analysis.
Fig. 11. (Color online) Simulated Bode plot at different load conditions with VBAT = 2.7 V, VIN = 1.35 V, and VOUT = 1.2 V.
Fig. 13. (Color online) The PSR simulation from VIN to VOUT under various loads.
Fig. 15. (Color online) Measured quiescent current and current efficiency vs. load current.
Fig. 16. (Color online) Measured voltage regulations. (a) Line regulation and (b) load regulation.
Fig. 17. (Color online) Measured PSR. (a) From VIN to VOUT and (b) from VBAT to VOUT.
Fig. 18. (Color online) Measured transient results under different load step configurations with CL = 0 pF, VIN = 1.35 V, VBAT = 2.4 V, and VOUT = 1.2 V. (a) With a load step of 5−205 mA. (b) With a load step of 5−95 mA.
Table 1. Comparison with the state-of-the-art OCL-LDOs.
View tableView in ArticleTable 1. Comparison with the state-of-the-art OCL-LDOs.
JSSC 2020[ 17 ]JSSC 2021[ 18 ]TCAS-I 2022[ 20 ]TPEL 2022[ 15 ]ESSCIRC 2023[ 16 ]This work FoM = TRECOVERY·(ΔVOUT/VOUT)·(IQ/ΔILOAD)[ 22 ]. a: IQ = 160 nA is utilized for FoM calculation, as the transient response performance for this FoM is at 1 mA ILOAD where IQ is 160 nA.Technology 65 nm 65 nm 0.5 µm 40 nm 55 nm 65 nm Power-MOS PMOS PMOS PMOS PMOS NMOS NMOS Architecture Event-driven + CP Event-driven + CP Event-driven + digital Event-driven + digital Event-driven + CC-CP Event-driven + DSC-CP VIN (V) 0.5−1 0.5−1.2 3−6 0.6−1.2 1.2−1.8 0.85−3.3 VOUT (V) 0.45−0.95 0.45−1.15 2.7−3.3 0.55−1.15 0.8−1.2 0.8−1.4 CL 0−10 µF 0 N/A 150 pF 1 pF−10 nF 0−1 nF CTOT 42 pF 15 pF 220 pF N/A 120 pF 64 pF Max. ILOAD (mA) 105 50 50 200 35 230 IQ (μA) 4.9 0.31−0.5 0.01 6−550 16−35 0.41 Peak current efficiency 99.99% 99.99% 99.99% 99.7% 99.5%−99.9% 99.999% Load Reg. (mV/mA) 0.09 1 1.2 N/A 1 0.005 PSR (dB@Hz) N/A N/A N/A −13@1 M N/A −32@1 M ΔVOUT @ILOAD,MIN−ILOAD,MAX 88 mV @5 m−105 mA 150 mV @1 m−11 mA 75 mV @1 m−50 mA 140 mV @N/A 240 mV @0−35 mA 166 mV @5 m−205 mA ΔILOAD /Tedg 100 mA/10 ns 10 mA/15 ns 49 mA/10 ns 105 mA/1 ns 35 mA/2 ns 200 mA/10 ns Recovery time (ns) 65 300 60 6 N/A 30 FoM (ps) 0.560 3.5 0.0045 0.147 N/A 0.0085
Tools
Get Citation
Copy Citation Text
Yiling Xie, Baochuang Wang, Dihu Chen, Jianping Guo. An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump[J]. Journal of Semiconductors, 2024, 45(6): 062203
Paper Information
Category: Articles
Received: Jan. 4, 2024
Accepted: --
Published Online: Jul. 8, 2024
The Author Email: Jianping Guo (JPGuo)
© Copyright 2018-2021 | Chinese Laser Press.
All Rights Reserved 沪ICP备15018463号-20