Modern system-on-a-chip often integrates various function blocks, such as digital, radio-frequency (RF), and noise-sensitive mixed-signal/analog circuit blocks. As these blocks may operate under different workloads, experiencing high demand, low demand, or retention modes, it is necessary to power each system under granular power management strategy^[1−3], to enhance the system power efficiency and some other performance like transient response and power supply rejection (PSR). Due to the good merit of low noise/ripple and fast transient response, low dropout regulators (LDOs) are good candidates for powering the noise-sensitive mixed-signal/analog circuits or fast digital circuits. Traditional LDOs typically rely on a bulky off-chip capacitor, typically in the μF range, to ensure stability and facilitate transient recovery^{[3, 4]}. However, this is not the preferred choice for on-chip applications that incorporate numerous voltage regulators, as the chip area, the external component, and the printed circuit board (PCB) volume, are all increased. Moreover, the transient behavior will also be degraded due to the parasitic effect from the bonding. Consequently, in the pursuit of miniaturization for portable or implantable devices, there is an increasing need for low power, rapid response, and fully integrated linear regulators ^[5−14].

Output-capacitorless low-dropout regulators (OCL-LDOs) are widely utilized in portable devices or implantable devices, ensuring a stable output voltage without the need for an external capacitor. High-efficiency internet of things (IoT) devices operate in standby mode most time^[9]. To prolong battery life, it is crucial to employ LDOs exhibiting ultralow quiescent current (I_Q). Nevertheless, these LDOs must still demonstrate swift transient response during state transitions and deliver exceptional dynamic performance when actively operating.

Diverse methodologies have been reported for achieving rapid transient response^[3−17] or low I_Q^[18−20]. Adaptive current biasing techniques^{[4, 6, 7, 10, 11]}, illustrated in Fig. 1(a), not only facilitate the maintenance of reducing quiescent current during steady-state operation but also promptly augment the bias current of the error amplifier to enhance transient response during transient events. However, the efficacy of this technique is constrained by the fact that the increased bias current is not entirely dedicated to push−pull operations in the power transistor, resulting in a limited improvement in slew rate, as observed in Ref. [11]. Furthermore, the excessively low output voltage resulting from this undershoot has the potential to result in system failure.

To further enhance the transient performance with low-power property, event-driven charge pump (CP), as shown in Fig. 1(b), has been introduced^{[16−18, 21]}. This architecture maintains a closed state during steady-state operation, effectively minimizing quiescent current, and directly injects transient current into the gate of the power transistor during transient events, significantly enhancing slew rate. However, as reported in Ref. [18], the triggering signal of the charge pump experiences a delay introduced by the period of oscillation (1/f₀) to trigger the phase-frequency detector, resulting in a reduced startup speed. To circumvent considerations of the nonlinear factors from the voltage-controlled oscillator and phase-frequency detector, the loop bandwidth of the LDO is constrained below f₀. Furthermore, the discrete-time integration of the charge pump introduces a pole at DC, necessitating that the output pole of the LDO must remain outside the loop bandwidth to ensure stability. However, under light load conditions, the output pole inevitably shifts to the left, potentially causing circuit instability. To enhance phase margin, it becomes necessary to reduce the strength of the charge pump, yet this compromises its potential to fully exploit transient performance improvement. Consequently, the observed undershoot in this LDO is 150 mV/10 mA, rendering its transient performance almost impractical. Notably, to prevent the output pole from entering the loop bandwidth, the LDO cannot accommodate capacitive loads, imposing severe limitations on its practical utility.

In Ref. [17], a rapid event-driven CP is employed, directly triggered by variations in the output voltage. This leads to a significant enhancement in transient response. Nevertheless, it also introduces new challenges to stability. To ensure stability, an AC-coupled high-impedance feedback loop is utilized to suppress the overflow current of the PMOS power transistor^[17]. Thus, a portion of the stability issues associated with the incorporation of CP is addressed. However, the delay associated with the transient detection circuit, an intrinsic factor in low-power design, was not considered in Ref. [17]. When accounting for the delay related to the detection circuit, the stability of LDO may be compromised due to excessive overflow current. The NMOS power transistor structure, implemented with an event-driven charge pump, is reported in Refs. [16, 21]. This configuration eliminates the need for intricate frequency compensation^[17]. A capacitively-coupled charge pump (CC-CP) loop that reacts swiftly to rapid variations in load currents which can dramatically improve the transient response is presented^{[16, 21]}. However, it is worth noting that this CC-CP loop exhibits a uniform response to any changes in load currents, potentially leading to over-regulation.

Based on the above considerations, we will focus on analyzing the performance trade-offs observed in prior CP-NMOS LDOs in this paper. Building upon this analysis, an innovative dual-loop NMOS LDO with an event-driven charge pump based on dynamic strength control is proposed. This design aims to achieve fast transient response, ultra-low power consumption, and a wide load dynamic range concurrently.

The organization of this paper is as follows. Section 2 discusses the advantages and disadvantages of the traditional CP-NMOS LDO, providing an analysis of the design trade-offs associated with transient response, stability, and power consumption. Section 3 introduces the overall structure of the proposed LDO, presenting a detailed overview of the design concept, circuit implementation, and operation principles of the key circuit blocks. The chip measurement results are presented in Section 4. Finally, a summary is made in Section 5.

To enhance the transient response of LDOs, the NMOS power transistor featuring higher carrier mobility is often employed. The smaller gate capacitance of an NMOS power transistor, in contrast to a PMOS, results in a higher frequency pole associated with the gate of the power transistor. This facilitates an accelerated slew rate (SR) in response to load transients and leads to a broader loop unity gain bandwidth (UGB). Furthermore, the NMOS power transistor's source follower feature inherently yields a low output impedance, mitigating stability issues associated with varying loads. Given the unity gain from gate to source in an NMOS power transistor without phase-shifting, it demonstrates superior stability control within the CP loop compared to the PMOS power transistor in Ref. [17], as there is no right half plane zero (RHZ). Additionally, the NMOS LDO inherently provides better PSR. Generally, it is convenient to provide separate voltage supplies for NMOS LDO in a battery-powered system. As depicted in Fig. 2(a), ensuring the proper operation of NMOS requires supplying a higher gate voltage (V_G), a condition is achievable by energizing both the error amplifier and the charge pump using the battery (V_BAT), and the input voltage (V_IN) of the LDO is often generated after a switching regulator for high power efficiency. Fig. 2(a) illustrates the circuit diagram of a conventional NMOS LDO with an event-driven CP loop. During transient instances, i.e., an event occurs, the power transistor is propelled by a pair of charge pumps to enhance transient response. These charge pumps, in turn, are activated by a pair of voltage comparators responsible for establishing the adjustment boundaries for the voltage threshold (V_H and V_L). Nevertheless, this traditional structure necessitates compromises in stability, transient response, and power consumption.

As illustrated in Fig. 2(b), phase A is dedicated to the self-adjustment of the NMOS. The presence of the capacitor (C_G) at V_G plays a crucial role in mitigating the coupling effect of C_GS, thereby effectively minimizing the undershoot of V_OUT. Phase B involves the swift elevation of V_G facilitated by the charge pump, contributing to the ultra-fast recovery of V_OUT. In Phase C, precise V_OUT adjustment is carried out by the error amplifier (EA) to ensure accurate regulation of V_OUT. It is noteworthy that a larger charging/discharging current (I_G) of CP and a quicker response speed lead to a shorter recovery time of V_OUT. However, in the case of a fast CP loop with high I_G, comparators with substantial power consumption become indispensable. Otherwise, instability may arise due to the delay in the CP loop, particularly the close delay (t_D). Using undershoot as an example, the charge pump exerts a rapid pull on the gate of the NMOS power transistor, causing a swift rise. In an ideal scenario, the charge pump should deactivate when V_OUT reaches V_L. However, due to the delay (t_D) of the comparator, V_OUT might be pulled up to V_H, triggering the charge pump once more and resulting in oscillation. It has been demonstrated that the CP loop can be stable only when the product of the slope of V_OUT and t_D does not exceed the threshold of the detection circuit. Since V_OUT follows V_G, the slope of V_OUT is equivalent to the slope of V_G, which is I_G/C_G. Therefore, it is essential to ensure that this slope, when multiplied by t_D, remains below the threshold of the detection circuit to maintain the stability of the CP loop. In summary, the instability caused by this condition can be represented by t_D × I_G/C_G > V_H – V_L. The V_H – V_L is defined as the regulation dead zone. A larger regulation dead zone, a shorter t_D, and a smaller charge pump current I_G all contribute to enhanced stability. Nevertheless, these enhancements come with trade-offs: a compromise on the precision of CP modulation, an increase in power consumption, and prolongation of recovery times. Thus, there exists a delicate balance among I_G, the regulation dead zone, and t_D. In this paper, a CP with dynamic strength control for NMOS OCL-LDO is proposed to effectively address these tradeoffs. The main architecture and operational principle will be explained in Section 3.

Fig. 3 provides a circuit architecture diagram of the proposed OCL-LDO. The construction of this dual-loop LDO is grounded in the traditional LDO discussed in Section 2. It includes a fast event-driven CP loop, incorporating the low-power transient detection circuit, dynamic strength control circuit, inner voltage regulator, and the current-source charge pump. This loop is utilized to effectively manage fast and considerable load variations. The introduction of a dynamic strength control charge pump (DSC-CP) addresses the inherent trade-offs in traditional CP-based LDOs by dynamically adjusting I_G during transient periods. Furthermore, it incorporates a high-accuracy adjustment loop, which involves an error amplifier with dynamic biasing.

The introduction of the proposed DSC-CP circuit in this paper extends the tolerance for prolonged t_D, enabling the implementation of a low-power transient detector. As a result, the transient detection circuit is no longer required to establish precise voltage detection thresholds. Consequently, conventional voltage comparators, which frequently compromise significant current for precise voltage detection thresholds and high speed, are not necessary. Instead, this circuit utilizes a comparator based on current, providing quicker comparison speed, lower power consumption, and a smaller regulation dead zone, as detailed in Section 3.2. A reduced regulation dead zone enables finer modulation of the event-driven CP loop. The current-based low-power transient detector is powered by an internal regulator with a 1-V supply. The high-level value of its output signals DN or UP ensures the operation of M_DO in the saturation region. The output current of M_DO and M_UP will become more controllable to their gate voltage and insensitive to their drain voltage (V_G). The operating principles of DSC-CP will be explained in Section 3.1. The implementation of the transient detection circuit and the dynamic error amplifier will be explained in Section 3.2 and Section 3.3, respectively. The analysis of stability and PSR will be conducted in Section 3.4.

Illustrated in Fig. 4(a), the schematic of the proposed dynamic-strength event-driven charge pump includes both the DSC circuit and a current-source charge pump. The DSC circuit, consisting of AC-coupling capacitors (C_UP, C_DO), DC-biased resistors (R₁, R₂), and M_N1-M_N3, M_P1-M_P3. Additionally, the current-source charge pump comprises M_UP and M_DO, which will be introduced later. The DSC-CP circuit employs thick-oxide I/O transistors, with the channel represented by a thicker line in the figure. The dynamic strength circuit adaptively adjusts the charge pump strength according to the output voltage recovery process, transforming the digital signal into an analog signal characterized by continuous variations in the effective level. Its operational principles are described as follows. At steady state, M_P2, M_P3, and M_N3 establish a high impedance at the gate of M_DO, thereby enhancing the coupling efficiency of C_DO. In the event of an overshooting V_OUT, a rising-edge DN signal is generated by the transient detection circuit. Through C_DO, DN is coupled to the gates of M_N3 and M_DO. Consequently, V_G can be promptly pulled down by M_DO, facilitating a fast recovery of V_OUT. Simultaneously, M_N3 drives the gate voltage of M_P3 low, establishing a low-impedance route from M_DO’s gate to V_SS. This results in an attenuation of the impedance of M_DO’s gate and a subsequent decrease in I_G. Once V_OUT has recovered, the falling-edge of the DN signal couples M_DO’s gate to a negative voltage, thereby halting the operation of CP. Due to the presence of C_DO, this negative voltage can be retained in M_DO’s gate for a duration significantly exceeding t_D. When the next DN signal comes, the voltage level of M_DO’s gate is still maintained negative voltage level. This results in a diminished pull current I_G compared to the previous one to ensure the stability of CP. As I_G decreases with each trigger of CP within a short period, the system will eventually converge to t_D × I_G/C_G > V_H – V_L after multiple triggers. As shown in Fig. 4(b), upon successive triggers, the circuit's output voltage demonstrates a gradual self-attenuation trend. The effective level applied to the subsequent circuit can be viewed as a continuously attenuating envelope curve, thereby aiding in the convergence of the system. Employing the DSC-CP mechanism ensures that the proposed LDO consistently achieves an optimal recovery rate, even when paired with a detection circuit featuring a small regulation dead zone and slow speed.

In Section 2, we have discussed the relationship between charge pump adjustment strength and the system's transient response performance and stability. The adjustment strength of the charge pump determines the transient response performance and stability of the output voltage. If the charge pump adjustment strength is too large, resulting in a large compensation current, the output voltage may change rapidly, leading to potential over-compensation in some cases. The M_UP and M_DO of the current-mode charge pump may have different threshold voltages under process, voltages, and temperature (PVT) variations, which could result in different adjustment strengths. For example, in some cases, if V_TH is too small, it may lead to an excessively strong initial strength from the charge pump. This can potentially result in over-compensation and multiple overshoots/undershoots. Such scenarios could pose stability issues for the traditional constant-strength charge pumps. This is because traditional current-mode charge pumps switch between the cutoff and linear regions of the transistor, and the compensation current remains fixed. This fixed compensation current cannot adapt to various load change scenarios. Fortunately, with the DSC-CP circuit proposed in this paper, the strength of the charge pump will gradually adaptively attenuate to an appropriate value, ensuring the stability of the system. Fig. 5 illustrates the sensitivity of PVT for transient response at temperatures of −40, 27, and 85 °C, and the process corners of tt, ss, and ff, respectively. It demonstrates that the proposed dynamic adjustment of charge pump strength and gradual attenuation mechanism can ensure stability even across PVT variations.

Fig. 6 demonstrates a contrast of simulated transient waveforms under different configurations. As shown in Fig. 6(a), the recovery time of the LDO would be slow without CP. As illustrated in Fig. 6(b), despite the ultra-fast response speed exhibited by an LDO with a traditional CP, stability issues arise due to the delay in the detection circuit. In Fig. 6(c), it is evident that the proposed LDO not only resolves the stability issue but also exhibits a rapid recovery speed.

As illustrated in Fig. 7, a fast and low-power current-based transient detection circuit is proposed, employing core transistors. Under static conditions, since I_DP9 is four times that of I_DN12, the drains of M_P9 and M_N12 are pulled to V_{DDL_A}. And DN is inverted to V_SS. Likewise, the drains of M_P10 and M_N13 are pulled to V_SS and UP is inverted to V_{DDL_B}. Figs. 7(a) and 7(b) illustrate the transient working principle with V_OUT undershoot and overshoot respectively. This principle will be explained with the example of V_OUT undershoot. The V_OUT with undershoot couples through C_t1 and C_t2 to the gates of M_P9,10 and M_N12,13. Since the drain of M_N12 is already at V_{DDL_A}, it remains unchanged, and DN remains at V_SS. Conversely, due to the decrease in the gate voltage of M_P10 and M_N13, their drains change from V_SS to V_{DDL_A}, then UP changes from V_{DDL_B} to V_SS.

The low-power and compact auxiliary inner voltage regulator, as depicted in Fig. 8(a), is employed to provide 1-V supplies (V_{DDL_A} and V_{DDL_B}) for the transient detection circuit to minimize total power consumption. The inverting chain can introduce considerable interference to the supply voltage. Therefore, the current comparator and the inverter driver chain are independently powered by a single LDO with split outputs. V_{DDL_A} provides a steady and clean source for the current comparator while V_{DDL_B} provides transient current for the drivers. This separation helps alleviate the demands on speed while maintaining detection accuracy, contributing to the achievement of low-power design.

As illustrated in Fig. 8(b), the proposed current source CP, which can precisely control I_G, is more area-efficient compared to the traditional CP. Through the inner voltage regulator, adjusting V_{DDL_B} to the voltage level of |V_GS| allows the current-source CP to require only one transistor.

In this design, the high-accuracy adjustment loop consists of an error amplifier, which also employs dynamic biasing technique. The proposed dynamic error amplifier is shown in Fig. 9(a). Following a transient trigger, the error amplifier dynamically boosts its bias current to expedite precise voltage regulation. Upon detecting transient changes in the load, whether it is an overshoot or an undershoot, V_BO is set to a high logic level. The activated M_N6 causes a rapid decrease of V_BP to V_SS and an increase of V_BN2 to V_BAT. Since the bias voltage for M_P3 and M_P4 is V_BP, when V_BP is pulled down to V_SS, M_P3 and M_P4 enter the linear region. Simultaneously, due to the bias voltage for M_N4 and M_N5 being V_BN2, when V_BN2 is raised to V_BAT, M_N4 and M_N5 also enter the linear region. As a result of the voltage division across diode-connected NMOS transistors, V_BN1 increases to an appropriate high level. Interestingly, at this moment, the EA can be simplified as Fig. 9(b). The described bias changes lead to M_P3, M_P4, M_N4, and M_N5 entering the linear region, and M_N1 transitioning from the subthreshold region to the saturation region. When V_BO is deactivated which means the process of the charge pump is finished, V_BP will slowly recover to an appropriate bias, V_BAT – V_SG,MP5. Due to the presence of gate capacitance C₀ and the diode-connected transistor M_P5, which has a higher pull-up resistance compared to the switching transistor M_N6, the recovery of V_BP is slow. It is noteworthy that the recovery of V_BP is slow, allowing the error amplifier to first rapidly adjust V_G and eventually precisely regulate V_G during the recovery process.

The proposed OCL-LDO features two loops: a high-accuracy loop for precise output voltage regulation and a fast event-driven charge pump loop aimed at enhancing transient response performance. The proposed fast event-driven charge pump loop operates on an event-driven basis and is closed at the steady state. As it primarily handles large signal responses, this loop can be disregarded in small signal analysis. Fig. 10 shows the small-signal model of the proposed LDO. g_EA and g_mp are the transconductances of EA and M_power. C_G and R_G are the capacitance and resistance at the gate of the power transistor. C_O and R_OUT are the load capacitance and resistance. Referring to the small-signal model in Fig. 10, the transfer function T(s) can be formulated as follows,

1T(s)=

where z1=gmpCGS, p1=1RGCG, p2=gmpCO, and gmp=2μnCox(WL)ILOAD. If C_O and C_GS are approximately equal in size, and z₁ and p₂ can cancel each other out, then the loop has only one dominant pole, making it stable. If C_O is large, the loop will have two poles, with p₁ being the dominant pole and p₂ being the secondary pole. Under light load conditions, g_mp is smaller, causing p₂ to be closer to the dominant pole. This situation poses the most severe stability concern. To verify the stability of the loop, Fig. 11 illustrates the phase margin under various loads, with a load capacitor of 100 pF. It can be observed that even under worst-case conditions, the phase margin remains at 80°.

To analyze the power supply rejection (PSR) performance, we extract the small-signal model in Fig. 12. PSR of a system, which is expressed as

2TPSR(s)=TPSROPEN1−T(s),

can be characterized by two transfer functions. The first one, T_PSROPEN (s), represents the open-loop PSR and signifies the gain from V_IN to V_OUT without any feedback loop. The second one, T (s), represents the transfer function of the entire loop. For T_PSROPEN, compared to PMOS power transistors, NMOS power transistors exhibit a lower T_PSROPEN gain. It is given as:

3TPSROPEN=ROUT||(sCO)−1||gmp−1ROUT||(sCO)−1||gmp−1+ro≈ROUT/rosCOROUT+gmpROUT+1≈1/gmpro1+s/p2,

where r_o is the on-resistance of the power transistor. Combining Eqs. (1)–(3), the PSR transfer function can be expressed as follows:

4TPSR(s)=voutvin=1/gmpro1+s/p2×11+gEA×RG×(1+s/z1)(1+s/p1)×(1+s/p2)1/gmpro1+s/p2.

As can be observed, despite the relatively low loop bandwidth of only 10 kHz, the PSR performance remains favorable due to the characteristics of the NMOS. Fig. 13 illustrates the simulation of the PSR from V_IN to V_OUT under various loads. The simulation results show that the PSR is also close to –30 dB at 1 MHz.

The proposed OCL-LDO was implemented in a 65 nm CMOS technology, and the chip micrograph is depicted in Fig. 14. The active area, including the test circuit, is 370 μm × 220 μm. The implemented LDO provides a regulated V_OUT of 0.8–1.4 V from a V_IN range of 0.85–3.3 V. This LDO exhibits a minimal dropout voltage (V_dropout) of 50 mV at 1.2-V V_OUT. Fig. 15 illustrates the varying I_Q under different loads and the corresponding current efficiency across varied loads. It is observed that the measured I_Q is below 410 nA, and the peak current efficiency reaches 99.999%. Fig. 16(a) illustrates the output voltage variation with input voltage (V_IN) under different output voltage conditions at I_LOAD = 200 mA. When the reference voltages are 0.8, 1, 1.2, and 1.4 V, their line regulations are 1.2, 1.39, 0.83, and 2.4 mV/V, respectively. Additionally, Fig. 16(b) demonstrates the load regulations under the V_OUT range of 0.8 to 1.4 V with V_dropout = 100 mV. The worst load regulation is 0.005 mV/mA. As shown in Fig. 17(a), the measured PSR from V_IN to V_OUT is –32 dB even at 1 MHz thanks to the NMOS power transistor. Due to the compensation capacitance C_G at the gate of the power transistor, the influence of V_BAT on V_OUT through the error amplifier is greatly reduced. As shown in Fig. 17(b), it can be observed that the PSR from V_BAT to V_OUT is lower than –40 dB, making it negligible compared to the PSR from V_IN to V_OUT.

Fig. 18 displays the transient response under different load steps, with C_L = 0 pF and ∆I_LOAD of 90 and 200 mA. Fig. 18(a) depicts a load step between 5 and 205 mA. With V_IN = 1.35 V, V_BAT = 2.4 V, and V_OUT = 1.2 V, the measured undershoot and overshoot voltages are 166 and 140 mV, respectively, as the load current varies within the specified range with a 10 ns edge time. The corresponding recovery times for undershoot and overshoot are 30 and 50 ns, respectively. And Fig. 18(b) depicts a load step of 5 to 95 mA. With V_IN = 1.35 V, V_BAT = 2.4 V, and V_OUT = 1.2 V, the measured undershoot and overshoot voltages are 138 and 132 mV, respectively, as the load current varies within the specified range with a 10 ns edge time. The corresponding recovery times for undershoot and overshoot are 50 and 30 ns, respectively. Irrespective of whether the load current changes between light and medium or between light and heavy, V_OUT can achieve recovery within 50 ns.

The measured performance of the proposed LDO is summarized in Table 1 and compared with recent state-of-the-art OCL-LDOs. The proposed LDO achieves fast transient response and recovery speed reliably with 410 nA I_Q. Simultaneously, it maintains favorable static characteristics.

In this paper, we have presented an NMOS LDO with dual-loop regulation. A fast event-driven charge pump loop with dynamic strength control is proposed to achieve high power efficiency and fast transient response, especially, short recovery time. The large-signal stability problem that has been ignored in the previous event-driven charge pump structure is solved with the proposed dynamic strength control circuit, breaking the performance trade-offs in the conventional structure. So that the potential of the charge-pump structure can be fully utilized for enhancing transient recovery. Furthermore, a dynamic error amplifier is used to realize the high-precision regulation for steady-state V_OUT, resulting in a good static characteristic.