[1] International Roadmap for Devices and Systems. Lithography[R](2022).

[2] Wei Y Y[M]. Theory and application of advanced lithography for VLSI(2016).

[3] Qiu J, Yang G H, Li J et al. Development and challenges of lithographical alignment technologies[J]. Acta Optica Sinica, 43, 1900001(2023).

[4] Cao J, Yang W H, Liu Z X et al. Controlling edge placement error in extreme ultraviolet lithography[J]. Chinese Journal of Lasers, 51, 0701005(2024).

[5] Kwak I, Kim N, Yim I et al. EPE-aware process optimization for scanner dose and overlay in DRAM use case[J]. Proceedings of SPIE, 12496, 124960N(2023).

[6] Zach F X, Cancheepuram S, Sah K et al. Multi-metrology: towards parametric yield predictions beyond EPE[J]. Proceedings of SPIE, 12496, 124960P(2023).

[7] Katz S, Grauer Y, Megged E. Optical overlay metrology trends in advanced nodes[J]. Proceedings of SPIE, 12053, 120530N(2022).

[8] Kubis M, Wise R, Chahine C et al. Reducing the impact of etch-induced pattern shift on overlay by using lithography and etch tool corrections[J]. Proceedings of SPIE, 10147, 101470H(2017).

[9] Feng Y B, Wu D A, Xuan P D et al. A novel accurate and robust technique in after-etch overlay metrology of 3D-NAND’s memory holes[J]. Proceedings of SPIE, 11325, 1132522(2020).

[10] Shchegrov A V, Leray P, Paskover Y et al. On product overlay metrology challenges in advanced nodes[J]. Proceedings of SPIE, 11325, 113251P(2020).

[11] Ma E Z, Zhang L B, Feng Y B et al. Overlay control solution for high aspect ratio etch process induced overlay error[J]. Journal of Vacuum Science & Technology B, 40, 042601(2022).

[12] Lin B J. Making lithography work for the 7-nm node and beyond in overlay accuracy, resolution, defect, and cost[J]. Microelectronic Engineering, 143, 91-101(2015).

[13] Owen D M. Stress inspection for overlay characterization[J]. Proceedings of SPIE, 8681, 86812T(2013).

[14] Brunner T, Menon V, Wong C et al. Characterization and mitigation of overlay error on silicon wafers with nonuniform stress[J]. Proceedings of SPIE, 9052, 90520U(2014).

[15] Tzai W J, Hsu S C C, Chen H et al. Techniques for improving overlay accuracy by using device correlated metrology targets as reference[J]. Journal of Micro/Nanolithography, MEMS, and MOEMS, 13, 041412(2014).

[16] Zhou G Y, Qi Y J, Li L et al. Robustness analysis method and simulation research of alignment mark[J]. Acta Optica Sinica, 43, 1113002(2023).

[17] Li L, Chen C, Zeng H et al. Analysis of diffraction-based wafer alignment rejection for thick aluminum process[J]. Journal of Vacuum Science & Technology B, 40, 022603(2022).

[18] Zhang Y, Zhang D W, Bian Y Y et al. Bottom grating asymmetry-induced inaccuracy in diffraction-based overlay measurement[J]. Journal of Micro/Nanopatterning, Materials, and Metrology, 21, 034001(2022).

[19] Ye L, Hu H Y, He W M. Image-based overlay (IBO) target segment design on self-aligned patterning process[J]. Proceedings of SPIE, 9778, 977828(2016).

[20] Lai L L, Qian R, Liu B Q et al. Study of alignment & overlay strategy in 14 nm lithography process[C], 1-3(2020).

[21] Koay C S, Hamieh B, Felix N et al. Reaching for the true overlay in advanced nodes[J]. Proceedings of SPIE, 10145, 101450B(2017).

[22] Meiling H. Role of EUV and its business opportunity[C](2016).

[23] Zhang L B, Dong L S, Su X J et al. New alignment mark designs in single patterning and self-aligned double patterning[J]. Microelectronic Engineering, 179, 18-24(2017).

[24] Du J Y, Dai F Z, Wang X Z. Calibration method for alignment error caused by asymmetric deformation of mark and its application in overlay measurement[J]. Chinese Journal of Lasers, 46, 0704004(2019).

[25] Li Y M, Yang L, Wang X H et al. Overlay metrology for lithography machine[J]. Laser & Optoelectronics Progress, 59, 0922023(2022).

[26] Chen X G, Wang C, Yang T J et al. Inline optical measurement and inspection for IC manufacturing: state-of-the-art, challenges, and perspectives[J]. Laser & Optoelectronics Progress, 59, 0922025(2022).

[27] Zhang L B, Lu C, Feng Y B et al. Overlay mark sub structure design to improve the contrast[C], 1-4(2020).

[28] Chen T Y, Zhou Y Y, Gao A. Research on wafer stage overlay-μDBO targets by lithography imaging simulation software[J]. Journal of Tsinghua University (Science and Technology), 63, 2057-2075(2023).

[29] Blancquaert Y, Dezauzier C. Diffraction based overlay and image based overlay on production flow for advanced technology node[J]. Proceedings of SPIE, 8681, 86812O(2013).

[30] Blancquaert Y, Dezauzier C, Depre J et al. Performance of ASML YieldStar μDBO overlay targets for advanced lithography nodes C028 and C014 overlay process control[J]. Proceedings of SPIE, 8681, 86811F(2013).

[31] Gao H Y, Chung W J, Aung N et al. Comparison study of diffraction based overlay and image based overlay measurements on programmed overlay errors[J]. Proceedings of SPIE, 9778, 97782Q(2016).

[32] Yang W H, Lin N, Wei X et al. Improving accuracy and sensitivity of diffraction-based overlay metrology[J]. Chinese Optics Letters, 21, 071204(2023).

[33] Zhou Y, Park D, Gutjahr K et al. Reducing the overlay metrology sensitivity to perturbations of the measurement stack[J]. Proceedings of SPIE, 10145, 101452G(2017).

[34] van Gardingen-Cromwijk T, Konijnenberg S, Witte S et al. Computational vibration mitigation using phase interpolation in digital holographic microscopy for overlay metrology[J]. Optics Express, 32, 36315-36328(2024).

[35] Qiu J, Qi Y J, Ma J et al. Characteristics of aperture in angle‑resolved scatterometer[J]. Acta Optica Sinica, 45, 0905001(2025).

[36] Chen X G, Hu J, Chen W L et al. Multi-spectral snapshot diffraction-based overlay metrology[J]. Optics Letters, 48, 3383-3386(2023).

[37] Meng K, Hu D Y, Wang K et al. Optimized overlay metrology based on polarization eigenstate of Mueller matrix[J]. Optics Express, 33, 13358-13375(2025).

[38] Porter C, Coenen T, Geypen N et al. Soft X-ray: novel metrology for 3D profilometry and device pitch overly[J]. Proceedings of SPIE, 12496, 124961I(2023).

[39] Zhang J H, Chen X G, Yang T J et al. X-ray-based overlay metrology using reciprocal space slicing analysis[J]. Optics Letters, 48, 6380-6383(2023).

[40] Inoue O, Kato T, Okagawa Y et al. In-die overlay metrology by using CD-SEM[J]. Proceedings of SPIE, 8681, 86812S(2013).

[41] Chung N Y, Maeng K S, Kim I et al. Interlayer 3D-EPE analysis using contour distance from design with high landing energy SEM imaging on advanced logic devices[J]. Proceedings of SPIE, 12955, 129550N(2024).

[42] Oya M, Okamoto Y, Nakazawa S et al. Utilization of active contour model with 3D-SEM simulation for see-through BSE image of high voltage SEM[J]. Proceedings of SPIE, 12955, 129550R(2024).

[43] Kim I H, Hyun C, Jo S et al. SEM overlay target design optimization by e-beam simulation[J]. Proceedings of SPIE, 12955, 129551I(2024).

[44] Hasumi K, Inoue O, Okagawa Y et al. SEM-based overlay measurement between via patterns and buried M1 patterns using high-voltage SEM[J]. Proceedings of SPIE, 10145, 101451J(2017).

[45] Jo S, Kim J, Park Y et al. SEM ADI on device overlay: the advantages and outcome[J]. Proceedings of SPIE, 12496, 124960K(2023).

[46] Mukherjee D, Sadeghian H, Nijmeijer H. Estimation of overlay error using in-line subsurface scanning probe microscopy[J]. Proceedings of SPIE, 12955, 129550Q(2024).

[47] Zhang L B, Lu C, Feng Y B et al. Method to improve the overlay image contrast and optimize the sub-segmentation mark[J]. Proceedings of SPIE, 11611, 1161131(2021).

[48] Lever J, Krzywinski M, Altman N. Principal component analysis[J]. Nature Methods, 14, 641-642(2017).

[49] Levinski V, Paskover Y, Aharon S et al. Spectral analysis overlay measurement approach for improvement of overlay accuracy in advanced integrated circuits[J]. Proceedings of SPIE, 12053, 120531Z(2022).

[50] Li Y L, Lim J, Park N et al. OPO improvements by Moiré effect-based imaging[J]. Proceedings of SPIE, 12496, 124960R(2023).

[51] Li L, Zhang Y X, Yu Q Y. Overview and prospect of virtual metrology technology for manufacturing processes[J]. Information and Control, 52, 417-431(2023).

[52] Mulkens J, Kubis M, Hinnen P et al. High order field-to-field corrections for imaging and overlay to achieve sub 20-nm lithography requirements[J]. Proceedings of SPIE, 8683, 86831J(2013).

[53] Yasuda M, Wakamoto S, Imagawa H et al. Stability and calibration of overlay and focus control for a double patterning immersion scanner[J]. Proceedings of SPIE, 7973, 79730Z(2011).

[54] Ifuku T, Hiura M, Takabayashi Y et al. Nanoimprint performance improvements for high volume semiconductor device manufacturing[J]. Proceedings of SPIE, 12293, 122930E(2022).

[55] Rui D H, Zhang L B, Shen H et al. Lithography mask thermal and stress effect for the machine overlay compensation[J]. Journal of Vacuum Science & Technology B, 42, 042601(2024).

[56] Horng S C. Compensating modeling overlay errors using the weighted least-squares estimation[J]. IEEE Transactions on Semiconductor Manufacturing, 27, 60-70(2014).

[57] Lee H, Han S J, Kim M et al. In-depth analysis of sampling optimization methods[J]. Proceedings of SPIE, 9778, 97781E(2016).

[58] Kim M S, Won H Y, Jeong J M et al. Reduction of wafer-edge overlay errors using advanced correction models, optimized for minimal metrology requirements[J]. Proceedings of SPIE, 9780, 97800A(2016).

[59] Zhang L B, Feng Y B, Song Z et al. Zernike model for overlay control and tool monitor for lithography and etch process[J]. Journal of Vacuum Science & Technology B, 40, 062604(2022).

[60] Slotboom D M, Hinnen P, Mulkens J. On-product overlay solutions for DUV and EUV mix-scanner usage in an EPE-driven patterning world[J]. Proceedings of SPIE, 12051, 120510L(2022).

[61] Moyne J R, Hajj H, Beatty K et al. SEMI E133: the process control system standard: deriving a software interoperability standard for advanced process control in semiconductor manufacturing[J]. IEEE Transactions on Semiconductor Manufacturing, 20, 408-420(2007).

[62] International Roadmap for Devices and Systems (IRDS). Virtual metrology white paper[R](2017).

[63] Kang P, Kim D, Lee H J et al. Virtual metrology for run-to-run control in semiconductor manufacturing[J]. Expert Systems with Applications, 38, 2508-2522(2011).

[64] Tin T C, Tan S C, Yong H et al. A realizable overlay virtual metrology system in semiconductor manufacturing: proposal, challenges and future perspective[J]. IEEE Access, 9, 65418-65439(2021).

[65] Lee H G, Schmitt-Weaver E, Kim M S et al. Virtual overlay metrology for fault detection supported with integrated metrology and machine learning[J]. Proceedings of SPIE, 9424, 94241T(2015).

[66] Schmitt-Weaver E, Subramony V, Ullah Z et al. Computational overlay metrology with adaptive data analytics[J]. Proceedings of SPIE, 10145, 101450V(2017).

[67] Ngo A T, Dey B, Halder S et al. Machine learning-based edge placement error analysis and optimization: a systematic review[J]. IEEE Transactions on Semiconductor Manufacturing, 36, 1-13(2023).

[68] Ophir B, Shusterman U, Golotsvan A et al. Machine learning for tool induced shift (TIS) reduction: an HVM case study[J]. Proceedings of SPIE, 11611, 116110E(2021).

[69] Su C H, Lin Z H, Lin Y S et al. Enhancement of diffraction-based overlay model for overlay target with asymmetric sidewall[J]. IEEE Transactions on Semiconductor Manufacturing, 33, 373-382(2020).

[70] Drissi Y, Gillijns W, Lee J U et al. SALELE process from theory to fabrication[J]. Proceedings of SPIE, 10962, 109620V(2019).

[71] Anunciado R, Lee J S, Barzegar E et al. Early defect detection for EUV self-aligned litho-etch litho-etch patterning with EPE[J]. Proceedings of SPIE, 12292, 122920J(2022).

[72] Decoster S, Lazzarino F, Vangoidsenhoven D et al. Exploration of EUV-based self-aligned multipatterning options targeting pitches below 20 nm[J]. Proceedings of SPIE, 10960, 109600L(2019).

[73] Venkatesan R, Guven C, Bhawe D et al. Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node[J]. Proceedings of SPIE, 12495, 124950D(2023).

[74] Chen Y J, Sun X Z, Song C Y et al. Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)[J]. Proceedings of SPIE, 12958, 1295802(2024).