Fig. 1. Overlay expected trends for different chips during the R&D process^[7]

Fig. 2. Overlay error induced by etch process in wafer outer edge areas^[8]. (a) Schematic of bending of etch plasma in the outer edge of wafer; (b) etch-induced overlay error during process transform; (c) SEM image of overlay mark and chip structure between wafer center and wafer edge after etch process; (d) overlay error distribution of M1A and M1B; (e) overlay error distribution along the radius directions of M1A and M1B

Fig. 3. Schematics of overlay error source in 3D-NAND multilayer process, and the possible overlay error distribution of ADI-AEI. (a) Overlay error and its main influence factors in different decks^[10]; (b) possible overlay error distribution after etch process between ADI and AEI within the wafer size range^[11]

Fig. 4. Schematic diagrams of sidewall deformation^[16]. (a) Sidewall angle deformation; (b) sidewall arc deformation

Fig. 5. Influences of overlay mark segmentations on image contrast, metrology accuracy, and overlay residues^[19]

Fig. 6. Experimental results that segmented-overlay mark may reduce the overlay accuracy and increase the overlay residues^[20]

Fig. 7. Lithography steps and critical alignment/overlay steps increase rapidly with the technology node development when using all immersion lithography methods^[22]

Fig. 8. Overlay residue comparison after using different feedback models and orders^[11]

Fig. 9. Schematics of overlay mark measurement by DBO technology and DBO algorithm to deal with the asymmetry and imbalance marks^[33]. (a) Principle of DBO measurement and possible asymmetry and imbalance mark structures; (b) method to improve the DBO accuracy for the asymmetry and imbalance marks

Fig. 10. Overlay measurement technology portfolio between optical measurement and SEM^[44]

Fig. 11. One recommended overlay feedback flow by adding SEM AEI overlay to verify the optical metrology errors^[45]

Fig. 12. Principal components analysis (PCA) method to deal with the asymmetry overlay mark optical metrology problems^[49]. (a) Examples of overlay mark asymmetry and overlay measured with different wavelengths; (b) illustration of overlay curves with PCA; (c) first six principal components signature across the wavelength spectrum

Fig. 13. Intrafield overlay feedback between k parameter and scanner actuator in ASML and Nikon. (a) ASML^[52]; (b) Nikon^[53]

Fig. 14. Overlay mark distributions during applying intra-field model, and different colors represent different chips in one exposure area^[2]. (a) Second-order intra-field model; (b) third-order intra-field model

Fig. 15. Overlay mark selection methods and residue comparison^[11]. (a) Quasi-circular random selection within the wafer range; (b) quasi-uniform random selection within the wafer range; (c) overlay residue of different correlation methods, where "Initial" means the original overlay, 1‒3 mean the overlay feedback order, and A, C, and U refer to the all overlay data, quasi-circular random overlay data, and quasi-uniform random overlay data

Fig. 16. Zernike-CPE model's flow and its results^[59]. (a) Flow of Zernike-CPE model; (b) effect of Zernike-CPE model; (c) relationship between Zernike order and overlay residual

Fig. 17. Virtual metrology applied in APC flow (R2R: run to run; FD: fault detection; VM: virtual metrology; Tgt: target)^[62]

Fig. 18. Virtual metrology applied in overlay error distribution prediction^[65]. (a) Virtual metrology model needed for the input and output map; (b) overlay measured, predicted and residual maps

Fig. 19. Flow of SALELE^[70]. (a) Divided design pattern to LE1 and LE2 according to the lithography process rule; (b) lithography is performed on the LE1 mask to obtain the trench structures LE1_Trenches; (c) spacer is deposited on the LE1_Trenches and LE1_Blocks mask is applied later to the LE1_final structures, and the maximum overlay is also shown in this sub-figure; (d) LE2_Threnches are performed after using lithography of LE2 mask; (e) LE2_Blocks mask is used to trim the LE2 patterns