Integrated circuit (IC) manufacturing technology is the foundation of modern society. Accurate fabrication of chip design patterns faces challenges in pattern resolution, layer-to-layer overlay accuracy, and manufacturing yield. In particular, overlay error in IC manufacturing has been the critical factor for chip yield improvement. It is crucial for engineers to gain a comprehensive understanding of overlay errors, including their causes, measurement methods, feedback algorithms, and control elements. This review examines the technical challenges in chip manufacturing overlay alignment, particularly focusing on advanced process requirements for overlay error specifications. We address issues such as process variations leading to decreased overlay precision, reduced measurement accuracy, and increased difficulty in matching error control. The paper systematically analyzes methods and algorithms for improving overlay accuracy and control quality. These include measurement techniques, compensation models, mark selection, artificial intelligence integration, and self-aligned processes. By examining the relationship between process variations and chip overlay errors, this review provides valuable references for China's IC equipment and process development, aiming to enhance chip manufacturing yield through multi-factor collaborative development.