Optoelectronic Technology, Volume. 43, Issue 4, 311(2023)

Design of MIPI D‑PHY High‑speed Channel with Offset Self‑calibration

Kai LIU1,2, Changbing QIN1,2, Baixue ZHANG1,2, Tingting XU1,2, and Qihong CHEN1,2
Author Affiliations
  • 1The 55th Research Institute of China Electronic Technology Group Corporation, Nanjing 2006, CHN
  • 2Nanjing Guozhao Photoelectric Technology Co., Ltd, Nanjing 11100, CHN
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    References(5)

    [1] Savolainen R, Rissa T. Standard interfaces in mobile terminals—Increasing the efficiency of device design and accelerating innovation[C], 592(2008).

    [3] MIPI Alliance[S](2014).

    [4] Enz C C, Temes G C. Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization[J]. Proc. IEEE, 84, 1584-1614(1996).

    [5] Rooijers T, Huijsing J, Makinwa K A A. A quiet digitally assisted auto-zero-stabilized voltage buffer with 0[C], 50-52.

    [8] Wu Shuangyi et al. An inductive peaking technology for high-speed MIPI receiver bandwidth expanding in a 90 nm CMOS process[C], 1-2(2016).

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    Kai LIU, Changbing QIN, Baixue ZHANG, Tingting XU, Qihong CHEN. Design of MIPI D‑PHY High‑speed Channel with Offset Self‑calibration[J]. Optoelectronic Technology, 2023, 43(4): 311

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    Paper Information

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    Received: Jul. 14, 2023

    Accepted: --

    Published Online: Mar. 21, 2024

    The Author Email:

    DOI:10.19453/j.cnki.1005-488x.2023.04.006

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