Photonics Research, Volume. 7, Issue 4, 437(2019)
25 Gbps low-voltage hetero-structured silicon-germanium waveguide pin photodetectors for monolithic on-chip nanophotonic architectures
Fig. 1. (a) Transversal schematics (
Fig. 2. (a) Static current-voltage (
Fig. 3. (a) Small-signal RF measurements of the
Fig. 4. Evolution of eye diagram apertures within a low-reverse-bias range at 10 Gbps, 20 Gbps, 25 Gbps, 28 Gbps, 32 Gbps, and 40 Gbps. Here,
Fig. 5. Bit-error-rate measurements of the Si-Ge-Si pin waveguide photodetector as a function of the input optical power. BER assessments performed (a) at 10 Gbps under low-reverse-bias states and (b) at 10 Gbps, 20 Gbps, and 25 Gbps, all biased at
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Daniel Benedikovic, Léopold Virot, Guy Aubin, Farah Amar, Bertrand Szelag, Bayram Karakus, Jean-Michel Hartmann, Carlos Alonso-Ramos, Xavier Le Roux, Paul Crozat, Eric Cassan, Delphine Marris-Morini, Charles Baudot, Frédéric Boeuf, Jean-Marc Fédéli, Christophe Kopp, Laurent Vivien, "25 Gbps low-voltage hetero-structured silicon-germanium waveguide pin photodetectors for monolithic on-chip nanophotonic architectures," Photonics Res. 7, 437 (2019)
Category: Silicon Photonics
Received: Nov. 30, 2018
Accepted: Jan. 24, 2019
Published Online: Apr. 11, 2019
The Author Email: Daniel Benedikovic (daniel.benedikovic@c2n.upsaclay.fr)