Frontiers of Optoelectronics, Volume. 6, Issue 3, 327(2013)

Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Bipin Kumar VERMA*, Shyam Babu SINGH, and Shyam AKASHE
Author Affiliations
  • Department of Electronics and Communication Engineering, ITM University, Gwalior (M.P.) 474001, India
  • show less
    References(18)

    [1] [1] Singh H, Agarwal K, Sylvester D, Nowka K J. Enhanced leakage reduction techniques using intermediate strength power gating. IEEE Transactions on Very Large Scale Integration (VLSI). ystems, 2007, 15(11): 1215-1224

    [2] [2] Johnson M, Somasekhar D, Chiou L Y, Roy K. Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Transactions on Very Large Scale Integration (VLSI). ystems, 2002, 10(1): 1-5

    [3] [3] Calimera A, Benini L, Macii A, Macii E, Poncino M. Design of a flexible reactivation cell for safe power-mode transition in powergated circuits. IEEE Transactions on Circuits and Systems I, Regular Papers, 2009, 56(9): 1979-1993

    [4] [4] Mutoh S, Douseki T, Matsuya Y, Aoki T, Shigematsu S, Yamada J. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE Journal of Solid-State Circuits, 1995, 30(8): 847-854

    [5] [5] Pakbaznia E, Pedram M. Design of a tri-model multi-threshold CMOS switch with application to data retentive power gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20(2): 380-385

    [6] [6] Shi K J, Howard D. Challenges in sleep transistor design and implementation in low-power designs. In: Proceedings of 43rd Annual Design Automation Conference. New York, 2006, 113-116

    [7] [7] Kudithipudi D, John E. Implementation of low power digital multipliers using 10 transistor adder blocks. Journal of Low Power Electronics, 2005, 1(3): 286-296

    [8] [8] Anuar N, Takahashi Y, Sekine T. 44-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. In: Proceedings of 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SOC). Madrid, 2010, 364-368

    [9] [9] Meher M R, Jong C C, Chang C H. A high bit rate serial-serial multiplier with on-the-fly accumulation by asynchronous counters. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(10): 1733-1745

    [10] [10] Kim S, Kosonocky S V, Knebel D R, Stawiasz K, Papaefthymiou M C. A multi-mode power gating structure for low-volyage deepsubmicron CMOS ICs. IEEE Transactions on Circuits and Wystems II, Express Briefs, 2007, 54(7): 586-590

    [11] [11] Chowdhury M H, Gjanci J, Khaled P. Controlling ground bounce noise in power gating scheme for system-on-a-chip. In: Proceedings of IEEE Computer Society Symposium on VLSI. Montpellier, 2008, 437-440

    [12] [12] Jiao H L, Kursun V. Ground bouncing noise suppression techniques for MTCMOS circuits. In: Proceedings of 1st Asia Symposium on Quality Electronic Design. Kuala Lumpur, 2009, 64-70

    [13] [13] Jiao H L, Kursun V. Ground bounce noise suppression techniques for data preserving sequential MTCMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(5): 763-773

    [14] [14] Jiao H L, Kursun V. Noise-aware data preserving sequential MTCMOS circuits with dynamic forward body bias. Journal of Circuits Systems and Computers, 2011, 20(1): 125-145

    [15] [15] Jiao H L, Kursun V. Ground-bouncing-noise-aware combinational MTCMOS circuits. IEEE Transactions on Circuits and Systems I, Regular Papers, 2010, 57(8): 2053-2065

    [16] [16] Kumar R, Kursun V. Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits. IEEE Transactions on Circuits and Wystems II, Express Briefs, 2006, 53(10): 1078-1082

    [17] [17] Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits. Proceedings of the IEEE, 2003, 91(2): 305-327

    [18] [18] Neil H E W, Harris D, Banerjee A. CMOS VLSI Design: A Circuit and System Perspective. 3rd ed. New Jersey: Pearson Education, 2011

    Tools

    Get Citation

    Copy Citation Text

    Bipin Kumar VERMA, Shyam Babu SINGH, Shyam AKASHE. Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier[J]. Frontiers of Optoelectronics, 2013, 6(3): 327

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category: RESEARCH ARTICLE

    Received: Apr. 10, 2013

    Accepted: Jun. 28, 2013

    Published Online: Mar. 3, 2014

    The Author Email: Bipin Kumar VERMA (bipinverma05@gmail.com)

    DOI:10.1007/s12200-013-0328-8

    Topics