The InP based terahertz monolithic integrated circuit （TMIC） have potentials for applications in plenty of fields，such as high-resolution security imaging systems^［1］，revolutionary communication networks^［2］，and radio astronomy^［3］. InP-based InGaAs/InAlAs HEMTs have demonstrated high operating frequency，low noise，high-gain performance，as well as good radiation resistance^［4］，making them an important device for InP based TMIC.

In recent years，the requirements for higher operation frequency and larger output power of TMIC result in a strong push of THz transistor technologies with current gain cutoff frequency （f_T） and maximum oscillation frequency （f_max）. The operating frequencies of integrated circuit amplifiers have seen corresponding increase to as high as 1 THz，with InP HEMTs reaching 1.5 THz f_max and 610 GHz f_T^［5］. And the recent literature reported the current record of f_T = 738 GHz with a gate length of 19 nm^［6］. Various efforts have been made to improve the f_T of InP based HEMTs，such as reducing the gate length （L_g）^［7］，source-to-drain spacing （L_SD）^［8］，and gate-to-channel distance （t_ins）^［9］，as well as optimizing the channel layer^［10-11］ and the gate recess^［12］. All the above measures are for minimizing the parasitic resistances，capacitances and increasing the transconductance.

In this letter，a narrow gate recess technology was used to optimize the parasitic resistances of InP based HEMTs. The In_0.53Ga_0.47As/In_0.52Al_0.48As HEMTs with gate length of 54.4 nm were fabricated. The values of f_T and f_{maxare as high as 441 GHz and 299 GHz，the maximum drain current IDS.max is 957 mA/mm，and the maximum transconductance gm.max is 1265 mS/mm. The InP based HEMTs with such high performances can be applied to terahertz monolithic integrated （TMIC） amplifiers and other circuits.}

The Schematic cross-section of InP-based HEMTs is shown in Fig. 1. The epitaxial layers of the devices were grown by Gas Source Molecular Beam Epitaxy （GSMBE） on 3 inch semi-insulating InP （100） substrates. From bottom to top，the layers consists of a 500-nm In_0.52Al_0.48As buffer layer，a 10-nm ln_0.53Ga_0.47As channel layer，a 3-nm unstrained ln_0.52Al_0.48As spacer layer，Si delta doping layer with 5×10¹² cm^-2 doping concentration，a 8-nm unstrained ln_0.52Al_0.48As Schottky barrier layer，a 4-nm InP etch-stop layer for preventing over etching and a 40-nm multi-layer cap layer that combines heavily-droped In_0.52Al_0.48As/In_0.53Ga_0.47As and a heavily-droped In_0.65Ga_0.35As upper cap layer. Hall measurements from a Hall calibration epitaxial layer structure were made at room temperature，showing a carrier mobility of over 10 000 cm²/（Vs）.

The fabrication process of InP HEMTs mainly contains five steps，including mesa isolation，ohmic contact formation，gate recesses，T-Gates，and connection pads，which is similar to our previously reported devices ^［13］. Isolating mesa was formed by phosphoric acid-based wet etching down to the InAlAs buffer layer. Source and drain electrodes were defined by electron beam lithography （EBL） with a 2.4-µm distance. Ti/Pt/Au （15 nm/15 nm/50 nm） was evaporated and lifted off to form the source and drain contacts，with contact resistance measured to be 0.023 Ω•mm and the specific contact resistivity 8.75E-8 Ω•cm² by TLM method.

Subsequently，the trilayer e-beam resist process was applied to fabricate 50-nm-gate-length T-gates. The gate process was developed by EBL with a PMMA/Al/UVIII （200 nm/10 nm/800 nm） resist stack，which is shown in Fig. 2. The top UVIII resist was exposed by a small dose and wide line. After that，the gate head was determined by TMAH development and rinsed in DI water. Subsequently，the gate foot was defined on a single layer of PMMA resist and was exposed by a big dose and narrow line. This approach allows better focusing at the gate foot exposure step because of the thin PMMA resist. As a result，this process scheme allows a small L_g. After that，the 200 nm gate recess was etched to InP etch-stop layer by H₃PO₄-solution，and a Ti/Pt/Au （25 nm/25 nm/350 nm） T-gate was evaporated and lifted off. The length of the T-Gate is 54.4 nm，as shown in Fig. 3. Finally，the Ti/Au （15 nm/400 nm） connection pads were evaporated for on-wafer DC and RF characteristics measurements.

DC properties were characterized by using a HP4142 semiconductor parameter analyzer at room temperature. Figure 4（a） shows the current-voltage （I-V） characteristics of the HEMT with L_g = 54.4 nm and gate width W_g = 2×50 μm at room temperature. The gate-source voltage （V_GS） is increased from -1.0 V to 0.0 V with step of + 0.2 V，and the drain-source voltage （V_DS） changes from 0 V to 1.2 V. The I_DS.max @ V_GS = 0.0 V is 957 mA/mm. The I_DS.max is enhanced compared to our previously reported InP HEMTs^［14］ and is attributed to the reduction of gate length. The device shows a small value of ON-resistance （R_{ON= 0.667 Ω•mm） due to a relatively narrow gate recess. Because the narrow gate recess leads to reduction of RS and RD^［15］. Moreover，the kink effect of the device is negligible due to the introduction of the InP etching-stopper layer.}

Figure 4（b） plots the measured transconductance （g_m） of the L_g = 54.4 nm device as a function of I_DS，for various vaules of V_DS from 0.1 V to 0.7 V in + 0.1 V steps. A maximum extrinsic transconductance g_m.maxof 1265 mS/mm is achieved at V_DS = 0.7 V. The pinch-off voltage is about -0.73 V at V_DS = 0.7 V as shown in Fig.3（c）.

The RF characteristics were measured using an Agilent E8363B PNA vector network analyzer from 0.1 GHz to 50 GHz. Before the RF test，the equipment was calibrated to eliminate systematic errors due to the environment or test equipment. In order to accurately obtain the S-parameter of the device，we calibrated the test reference surface to the GSG test probe tip. The open and short structures were used to substract pad-related capacitance and inductance components from measured S-parameters. Then，the values of a short-circuit current gain （H₂₁），a maximum available gain and a maximum stable gain （MAG/MSG），and a Mason’s unilateral gain （U） were plotted in Fig. 5（a）. The bias condition was at V_GS = -0.35 V and V_DS= 0.7 V.

Since the test frequency range was limited from 0.1 GHz to 50 GHz，we obtained a value of f_T = 441 GHz by extrapolating the measured H₂₁ with a slope of -20 dB/dec. Regarding f_max，it cannot be directly extracted from the measured U or MAG/MSG. This is because it is difficult to observe a decline in the MAG/MSG frequency curve with a slope of -20 dB/dec in a limited test range. Therefore，if the frequency curve of MAG/MSG is extrapolated with -20 dB/dec at 50 GHz，the f_max obtained is a conservative result. So，we constructed a small-signal model that yielded a well behaved U with a single-pole system，as shown in Fig. 5（b）^［16］. Using the small-signal model，the values of f_max = 299 GHz and f_T = 443 GHz were estimated accurately. The measured f_{T_measure} and the modeled f_{T_model} are similar，increasing the credibility of our model.

The f_T and f_max are expressed as equtions （1） and （2）：

Where C_gs and C_gd are the capacitances in between gate to source and gate to drain； R_g，R_S，and R_D are the parasitic resistances of gate，source and drain； g_mi is the intrinsic transconductance； g_ds is the conductance between drain and source.

Equations （1） and （2） suggest that C_gs，C_gd，R_S，R_D，g_miand g_ds are the key parameters that affect f_T and f_max. Table 1 shows small-signal model parameters. These key parameters are all related to the size of the gate recesse and gate length. In terms of f_T，the small gate length reduces capacitances and increases g_mi. At the same time，the narrow gate recess also reduces the R_S and R_D. So，these affects lead to a higher f_T = 441 GHz. However，the narrow gate recesse correspond to larger values of C_gd/C_gs，and the shorter gate length leads to larger R_g and g_ds，which leads to a smaller f_max = 299 GHz.

Figure 6 plots the extracted f_T as a function of I_DS for the same device at V_DS = 0.7 V，which consists with the g_m against I_DS in Fig. 4. The f_T of the device exceeds 400 GHz over a wide range of I_DS.

Table 2 shows the reported the performance of InGaAs/InAlAs HEMTs with L_g from 50 nm to 75 nm. What these devices have in common is that the channel of devices are indium-rich InGaAs. And Pt buried gate technology is used to decrease the gate-to-channel distance，resulting the excellent RF performance. Although the values of g_m.max and f_T are quite different，the larger g_m.max corresponds to higher f_{Tin this table. Compared with these results，our device achieved the fT of over 400 GHz with the lowest gm.max，and we need to improve fT through further increasing gm.max in the future.}

In summary，we have successfully designed and fabricated a 54.4 nm T-gate InGaAs/InAlAs InP-based HEMT with f_T > 400 GHz. In order to optimize the parasitic resistances，we adopt a narrow gate recess technology. As a result，the f_T reaches as high as 441 GHz with a g_m.max of 1265 mS/mm. The f_T is expected to be promoted through further increasing g_m.max by adopting an Indium-rich channel and a Pt buried gate technology.