Chinese Journal of Liquid Crystals and Displays, Volume. 40, Issue 3, 448(2025)

Design of heterogeneous FPGA hardware accelerator based on CNN

Haolin JI1,2,3, Wei XU1,3、*, Yongjie PIAO1,3, Xiaobin WU1,2,3, and Tan GAO1,2,3
Author Affiliations
  • 1Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033, China
  • 2University of Chinese Academy of Sciences, Beijing 100049, China
  • 3Key Laboratory of Space-Based Dynamic & Rapid Optical Imaging Technology, Chinese Academy of Sciences, Changchun 130033,China
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    References(16)

    [1] SIMONYAN K, ZISSERMAN A. Very deep convolutional networks for large-scale image recognition[J/OL](2014).

    [4] LIN Z H, COURBARIAUX M, MEMISEVIC R et al. Neural networks with few multiplications[C](2016).

    [5] MISHRA A, NURVITADHI E, COOK J J et al. WRPN: wide reduced-precision networks[C](2018).

    [6] ZHOU S C, WU Y X, NI Z et al. DoReFa-Net: training low bitwidth convolutional neural networks with low bitwidth gradients[J/OL](2016).

    [8] WEI C L, CHEN R L, GAO Q et al. FPGA-based hardware acceleration for CNNs developed using high-level synthesis[J]. Optics and Precision Engineering, 28, 1212-1219(2020).

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    Haolin JI, Wei XU, Yongjie PIAO, Xiaobin WU, Tan GAO. Design of heterogeneous FPGA hardware accelerator based on CNN[J]. Chinese Journal of Liquid Crystals and Displays, 2025, 40(3): 448

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    Paper Information

    Category: Circuit Design

    Received: Jul. 12, 2024

    Accepted: --

    Published Online: Apr. 27, 2025

    The Author Email: Wei XU (xwciomp@163.com)

    DOI:10.37188/CJLCD.2024-0198

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