Researching | Design of heterogeneous FPGA hardware accelerator based on CNN

Chinese Journal of Liquid Crystals and Displays, Volume. 40, Issue 3, 448(2025)

Design of heterogeneous FPGA hardware accelerator based on CNN

Haolin JI^1,2,3, Wei XU^1,3、*, Yongjie PIAO^1,3, Xiaobin WU^1,2,3, and Tan GAO^1,2,3

Author Affiliations

¹Changchun Institute of Optics， Fine Mechanics and Physics， Chinese Academy of Sciences， Changchun 130033， China

²University of Chinese Academy of Sciences， Beijing 100049， China

³Key Laboratory of Space-Based Dynamic & Rapid Optical Imaging Technology， Chinese Academy of Sciences， Changchun 130033，China

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Figures & Tables(9)

Fig. 1. Schematic diagram of convolutional layers

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Fig. 2. Schematic diagram of CNN accelerator architecture

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Fig. 3. SIMD multiplication using common operand C

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Fig. 4. SIMD CU structure diagram

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Fig. 5. （a） Data flow of convolutional kernels in PE units；（b）Input feature map data flow in PE unit.

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Fig. 6. SIMD buffer structure diagram

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Fig. 7. Analysis of parallelism in XC7Z020 Device

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Fig. 8. Implementation of embedded systems on ZYNQ devices

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Table 1. Comparison of implementation results of CNN accelerator proposed in this paper with that of other accelerators

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Table 1. Comparison of implementation results of CNN accelerator proposed in this paper with that of other accelerators

	FPGA平台（DSP总数）	频率/MHz	Gops	DSPs	DE/ （Gops/DSPs）	CONVs Time/ms	PEff/ （Gops·W^-1）
本文	XC7Z020（220）	150	90.1	216（98.1%）	0.417	382.2	38.5
文献［12］	XC7Z020（220）	150	84.3	190（86.3%）	0.443	364	24.1
文献［9］	XC7Z020（220）	125	48.53	220（100%）	0.22	633	27.7
本文	XC7Z045（900）	167	425.32	864（96.0%）	0.48	91.2	102
文献［10］	XC7Z045（900）	150	36.8	197（21.8%）	0.186	1639.3	79.7
文献［12］	XC7Z045（900）	214	137	780（86.6%）	0.175	224.6	14.2
文献［9］	XC7Z045（900）	125	155.81	855（95.0%）	0.182	249.5	38.8
文献［13］	XC7Z045（900）	150	374.98	900（100%）	0.416	82.03	NA¹
文献［14］	XC7Z045（900）	140	169	864（96.0%）	0.195	181.8	16.9
文献［11］	GX1150（1518）	200	715.9	1518（100%）	0.47	43.2	NA

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Haolin JI, Wei XU, Yongjie PIAO, Xiaobin WU, Tan GAO. Design of heterogeneous FPGA hardware accelerator based on CNN[J]. Chinese Journal of Liquid Crystals and Displays, 2025, 40(3): 448

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Paper Information

Category: Circuit Design

Received: Jul. 12, 2024

Accepted: --

Published Online: Apr. 27, 2025

The Author Email: Wei XU (xwciomp@163.com)

DOI:10.37188/CJLCD.2024-0198

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