Fig. 1. (Color online) (a) Half-cell structure and (b) multi-epi process of the VVD-SJ.

Fig. 2. (Color online) BV vs. K_CIB for (a) UD-SJ, (b) VVD-SJ with b = 0, (c) VVD-SJ with a = 0, (d) VVD-SJ with a ≠ 0 and b ≠ 0.

Fig. 3. (Color online) E-field distributions of (a) UD-SJ, (b) VVD-SJ with a > 0 and b < 0, (c) VVD-SJ with a < 0 and b > 0 under different K_CIB.

Fig. 4. (Color online) R_on,sp vs. K_CIB for UD-SJ and VVD-SJ.

Fig. 5. The test circuit of dynamic avalanche energy.

Fig. 6. (Color online) The simulated gate−source voltage (V_gs), drain−source voltage (V_ds) and drain−source current (I_ds) waveforms of VVD-SJ during UIS process when (a) just failing and (b) obviously failing.

Fig. 7. (Color online) E_AS vs. K_CIB for (a) UD-SJ and (b) VVD-SJ.

Fig. 8. (Color online) Avalanche current with different K_CIB in the case of (a) UD-SJ, (b) VVD-SJ with a > 0 and b < 0, and (c) VVD-SJ with a < 0 and b > 0.

Fig. 9. (Color online) Temperature with different K_CIB in the case of (a) UD-SJ, (b) VVD-SJ with a > 0 and b < 0, and (c) VVD-SJ with a < 0 and b > 0.

Fig. 10. (Color online) W_C for (a) UD-SJ and (b) VVD-SJ with a = 0.2 and b = −0.2.

Fig. 11. The SEM images of (a) UD-SJ-MOS and (b) VVD-SJ-MOS with a = 0.2 and b = −0.2.

Fig. 12. (Color online) W_C for (a) UD-SJ and (b) VVD-SJ with a = 0.2 and b = −0.2.